Rino Choi

The effect of moisture on the photon-enhanced negative bias thermal instability in Ga–In–Zn–O thin film transistors

We investigated the impact of photon irradiation on the stability of gallium-indium-zinc oxide (GIZO) thin film transistors. The application of light on the negative bias temperature stress (NBTS) accelerated the negative displacement of the threshold voltage (Vth). This phenomenon can be attributed to the trapping of the photon-induced carriers into the gate dielectric/channel interface or the gate dielectric bulk. Interestingly, the negative Vth shift under photon-enhanced NBTS condition worsened in relatively humid environments. It is suggested that moisture is a significant parameter that induces the degradation of bias-stressed GIZO transistors.

The impact of gate dielectric materials on the light-induced bias instability in Hf–In–Zn–O thin film transistor

This study examined the effect of gate dielectric materials on the light-induced bias instability of Hf–In–Zn–O (HIZO) transistor. The HfOx and SiNx gated devices suffered from a huge negative threshold voltage (Vth) shift (>11u2002V) during the application of negative-bias-thermal illumination stress for 3 h. In contrast, the HIZO transistor exhibited much better stability (<2.0u2002V) in terms of Vth movement under identical stress conditions. Based on the experimental results, we propose a plausible degradation model for the trapping of the photocreated hole carrier either at the channel/gate dielectric or dielectric bulk layer.

The Impact of Device Configuration on the Photon-Enhanced Negative Bias Thermal Instability of GaInZnO Thin Film Transistors

We investigated the effect of device configuration on the light-induced negative bias thermal instability of gallium indium zinc oxide transistors. The V th of back-channel-etch (BCE)-type transistors shifted by ―3.5 V, and the subthreshold gate swing (SS) increased from 0.88 to 1.38 V/decade after negative bias illumination temperature stress for 3 h. However, etch-stopper-type devices exhibited small V th shifts of ―0.8 V without degradation in the SS value. It is believed that the inferior instability of the BCE device is associated with the formation of an interfacial molybdenum (Mo) oxychloride layer, which occurs in the course of dry etching Mo using Cl 2 /O 2 for source/drain patterning.

The Effect of Density-of-State on the Temperature and Gate Bias-Induced Instability of InGaZnO Thin Film Transistors

The impact of a gate insulator (GI) material on the device instability of InGaZnO (IGZO) thin film transistors (TFTs) was investigated. The IGZO TFTs with SiO 2 GI showed consistently better stability against the applied temperature stress and positive/negative gate bias stress than their counterparts with SiN x GI. This superior stability of the SiO 2 -gated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities. Based on the Meyer-Neldel rule, the total DOS energy distribution for both devices was extracted and compared, which can explain the experimental observation.

Improvement in both mobility and bias stability of ZnSnO transistors by inserting ultra-thin InSnO layer at the gate insulator/channel interface

This study examined the effect of the thickness of interfacial indium-tin oxide (ITO) on the performance and bias reliability of zinc-tin oxide (ZTO) thin film transistors (TFTs). The 3.5-nm-thick ITO-inserted ZTO TFTs exhibited superior mobility (43.2 cm2/V s) to that of the ZTO only TFTs (31.6 cm2/V s). Furthermore, the threshold voltage shifts for the ZTO/ITO bi-layer device decreased from 1.43 and −0.88 V (ZTO only device) to 0.46 V and −0.41 V under positive and negative bias stress, respectively. This improvement can be attributed to a decrease in the interfacial trap density for the ITO-inserted ZTO device.

Investigation of Light-Induced Bias Instability in Hf-In-Zn-O Thin Film Transistors: A Cation Combinatorial Approach

Thin Film Transistors: A Cation Combinatorial Approach Jang-Yeon Kwon, Ji Sim Jung, Kyoung Seok Son, Kwang-Hee Lee,* Joon Seok Park, Tae Sang Kim, Jin-Seong Park, Rino Choi, Jae Kyeong Jeong, Bonwon Koo, and Sangyun Lee Display Laboratory, Samsung Advanced Institute of Technology, Nongseo-Dong, Giheung-Gu, Yongin-Si, Gyeonggi-Do 446-712, Korea Department of Materials Science and Engineering, Dankook University, Anseo-Dong, Cheonan 330-714, Korea Department of Materials Science and Engineering, Inha University, Incheon 402-751, Korea

Ti-Doped Indium Tin Oxide Thin Films for Transparent Field-Effect Transistors: Control of Charge-Carrier Density and Crystalline Structure

Indium tin oxide (ITO) films are representative transparent conducting oxide media for organic light-emitting diodes, liquid crystal displays, and solar cell applications. Extending the utility of ITO films from passive electrodes to active channel layers in transparent field-effect transistors (FETs), however, has been largely limited because of the materials high carrier density (>1 × 10(20) cm(-3)), wide band gap, and polycrystalline structure. Here, we demonstrate that control over the cation composition in ITO-based oxide films via solid doping of titanium (Ti) can optimize the carrier concentration and suppress film crystallization. On 120 nm thick SiO(2)/Mo (200 nm)/glass substrates, transparent n-type FETs prepared with 4 at % Ti-doped ITO films and fabricated via the cosputtering of ITO and TiO(2) exhibited high electron mobilities of 13.4 cm(2) V(-1) s(-1), a low subthreshold gate swing of 0.25 V decade(-1), and a high I(on/)I(off) ratio of >1 × 10(8).

Effective surface passivation methodologies for high performance germanium metal oxide semiconductor field effect transistors

We demonstrate methodologies to improve the interface characteristics between a germanium (Ge) substrate and high-k gate dielectrics. GeON and SiOx were investigated as passivating layers on a Ge surface. Smaller hysteresis and interface state density (Dit) were obtained using SiOx interface layer and p-type metal oxide semiconductor field effect transistors (MOSFETs) fabricated with a gate stack of Ge/SiOx/HfSiO/WN showed about two times higher effective mobility compared to universal Si/SiO2 MOSFET. Because the formation of GeOx at the interface resulted in higher hysteresis and equivalent oxide thickness, the effective suppression of growth of unstable GeOx by SiOx interface layer contributed to the good device characteristics of the fabricated devices.

Improved Electrical Properties of Solution-Processed ZrO2 Gate Dielectric for Large-Area Flexible Electronics

Zirconium oxide (ZrO2), which has high dielectric constant, was investigated for application in flexible electronics. When the spun-cast film was annealed at a low temperature, the electrical properties were not encouraging because residual organic particles remained at the dielectric. To address this problem we used plasma annealing at a reasonably low temperature and achieved improved dielectric properties such as lower leakage current, higher dielectric constant, and better reliability. Auger depth profile spectroscopy results suggested reduction of carbon percentage at the dielectric. We demonstrated device application by fabricating transistor device with an organic channel layer. The transistor electrical properties were encouraging, exhibiting an electron mobility of 0.3 cm2/(V·s). The results were very promising and suggest that ZrO2 could be applied to all-printed electronic devices in the near future.

Bias polarity dependence of charge trapping behaviours in La-incorporated hafnium-based dielectric

Bias temperature instability of metal-oxide-semiconductor field effect transistors (MOSFETs) with various concentrations of La incorporation in Hf-based dielectrics was characterized by varying the magnitude and polarity of the stress biases. Contrasting dependences of charge trapping on the magnitude of the stress biases are shown by changing the bias polarity. A model based on the distortion of asymmetric energy band diagrams and La-induced interface dipoles is suggested to explain this behaviour. Change of gate leakage currents according to La-incorporation, magnitude, and polarity of bias stresses supports the validity of the model.