H.S. Momose

Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 /spl mu/m/spl times/0.75 /spl mu/m, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n/sup +/ polysilicon gates subjected to RTA at 1050/spl deg/C for 20 s and furnace annealing at 850/spl deg/C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications.

Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs

Ultra-high performance n-MOSFETs were fabricated with a tunneling gate oxide 1.5 nm thick. It was found that these devices operate well when the gate length is around 0.1 /spl mu/m, because gate leakage current falls in proportion to the gate length and the drain current increases in inverse proportion. A very high drivability of 1.1 mAspl mu/m at 15 V was obtained, even in devices with a 0.14 pm gate length. A record high transconductance, 1,010 mS/mm at room temperature was also obtained in 0.09 /spl mu/m MOSFETs. Confirmation was obtained that hot-carrier reliability improves as the gate oxide thickness is reduced, even in the 1.5 nm case. High current drive at the low supply voltage of 0.5 V was also demonstrated. We made clear that very high performance is obtained in Si MOSFETs, if we can use a high capacitance gate insulator. In future devices, the tunnel gate oxide may be a good candidate for such a gate film, depending upon their applications.<<ETX>>

High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs

Results of the high-frequency AC characteristics of 1.5 nm direct-tunneling gate oxide MOSFETs were shown for the first time. Very high cutoff frequencies of more than 150 GHz were obtained at gate lengths of sub-0.1 /spl mu/m regime due to the high transconductance. Excellent NF/sub min/ value of 0.51 dB was obtained at high-frequency operation of 2 GHz. Also, good operation of the 1.5 nm gate oxide CMOS ring oscillator has been confirmed.

A NiSi salicide technology for advanced logic devices

A nickel-silicide (NiSi) technology for deep submicron devices has been developed. It was confirmed that Ni films sputtered on n- and p-single and polysilicon can be changed to mono-silicide (NiSi) stably at low temperature (600 degrees C) over a short period without any agglomeration. The NiSi layer did not absorb boron or arsenic atoms during silicidation, and a high concentration of boron or arsenic was achieved at the silicide/silicon interface, contributing to a low contact resistance. NiSi technology was applied to a dual-gate CMOS structure. Excellent pn junction characteristics and high drivabilities of both the n- and p-MOSFETs were successfully obtained.<<ETX>>

Future perspective and scaling down roadmap for RF CMOS

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and small-signal equivalent circuit of the MOSFET, three intrinsic noise parameters (/spl gamma/, /spl delta/, and c) for the drain noise and induced gate noise are calculated. Validity and error analysis for the simulation are discussed by comparing the simulation results with theoretical results as well as measured data.

Control of charge dynamics through a charge-separation interface for all-solid perovskite-sensitized solar cells.

The relationship between the structure of the charge-separation interface and the photovoltaic performance of all-solid dye-sensitized solar cells is reported. This cell is composed of porous a TiO2/perovskite (CH3NH3PbI(x)Cl(3-x))/p-type organic conductor. The porous titania layer was passivated with Al2O3 or Y2O3 to remove surface traps of the porous titania layer. Both passivations were effective in increasing the efficiency of the solar cell. Especially, the effect of Y2O3 passivation was remarkable. After passivation, the efficiency increased from 6.59 to 7.5%. The increase in the efficiency was discussed in terms of the electron lifetime in TiO2, the thermally stimulated current, the measurement of the microwave refractive carrier lifetime, and transition absorption spectroscopy. It was proven that surface passivation resulted in retardation of charge recombination between the electrons in the porous titania layers and the holes in the p-type organic conductors.

Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration

The characteristics and reliability of nitrided-oxide gate n- and p-MOSFETs with less than 1 atom% nitrogen concentration in the gate films were investigated in detail. These very light nitridations were accomplished using NH/sub 3/ gas at low temperatures/spl minus/from 800/spl deg/ C to 900/spl deg/ C. Nitrogen concentrations as low as 0.13 atom% were successfully measured by SIMS and AES. The region of optimum nitrogen concentration for deep-submicron devices is discussed. We explain how good drivability and good hot-carrier reliability were attained simultaneously with a nitrogen concentration of around 0.5 atom%, which is equivalent to that of oxynitride gate MOSFETs using N/sub 2/O gas. The suppression of boron penetration is also discussed. Light nitridation by ammonia gas is particularly desirable for deep-submicron processes because it can be accomplished at a relatively low temperature of about 900/spl deg/C. >

Effects of boron penetration and resultant limitations in ultra thin pure-oxide and nitrided-oxide gate-films

The boron penetration effect was compared for p/sup +/ poly gate PMOSFETs with pure oxide gates and nitrided oxide gates. For a gate thickness of 6.5 nm, reduced boron dosage and rapid thermal processing solve the problem of boron penetration in the pure oxide case. However, when the film thickness is less than 6.5 nm, only a nitrided oxide film can solve the problem. From the results of EDX analysis in nitrided oxide films, it was found that nitrogen build-up at the interface is small and that a nitrogen concentration of only a few percent leads to complete suppression of boron penetration down to the 2 nm range of film thickness. Excellent characteristics in 2.6 nm nitrided oxide gate p-MOSFETs, free from boron penetration effects, were demonstrated.<<ETX>>

Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si substrate were investigated and compared with those on a [100] substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the [111] substrate is smaller than that on the [100] substrate and that of p-MOSFETs on [111] is larger than that on [100] until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for [100] and [111] substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the [111] substrate is slightly better than that on the [100] substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4/spl deg/ from [100] axis were investigated. It was found that there are few differences in the mobility between [100] and [100] 4/spl deg/ off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal [100] substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs.