H. Iwai

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFETs were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 /spl mu/m, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA//spl mu/m and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 /spl mu/m at room temperature. These are the highest values ever obtained with Si MOSFETs at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFETs if a high-capacitance gate insulator is used.

Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFETs was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFETs also operated at higher speed. >

Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions

Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Even in the sub-50 nm region, short-channel effects-V/sub th/ shift and S-factor degradation-are suppressed very well. The impact ionization rate falls significantly as Vd falls below 1.5 V. It is found that, in the case of Vd less than 1.5 V, hot-carrier degradation is not a serious problem even in the sub-50 nm region.<<ETX>>

Scaling the MOS transistor below 0.1 /spl mu/m: methodology, device structures, and technology requirements

This work is a systematic investigation of the feasibility of MOSFETs with a gate length below 0.1 /spl mu/m. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 /spl mu/m MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI. >

A NiSi salicide technology for advanced logic devices

A nickel-silicide (NiSi) technology for deep submicron devices has been developed. It was confirmed that Ni films sputtered on n- and p-single and polysilicon can be changed to mono-silicide (NiSi) stably at low temperature (600 degrees C) over a short period without any agglomeration. The NiSi layer did not absorb boron or arsenic atoms during silicidation, and a high concentration of boron or arsenic was achieved at the silicide/silicon interface, contributing to a low contact resistance. NiSi technology was applied to a dual-gate CMOS structure. Excellent pn junction characteristics and high drivabilities of both the n- and p-MOSFETs were successfully obtained.<<ETX>>

Temperature dependence of emitter-base reverse stress degradation and its mechanism analyzed by MOS structures

Different degradation modes were observed under high and low reverse stress current conditions. The temperature dependence of the gradation was studied, and it was found that the degradation is greatest around 50 degrees C. The mechanisms of the degradation and its recovery were also investigated, using MOS structures and simulation. MOSFET evaluation indicated that electron trapping and interface state generation occur during the stress. Simulation confirmed that the degradation is caused mainly by the interface states generated in the oxide near the emitter-base junction.<<ETX>>

Effects of boron penetration and resultant limitations in ultra thin pure-oxide and nitrided-oxide gate-films

The boron penetration effect was compared for p/sup +/ poly gate PMOSFETs with pure oxide gates and nitrided oxide gates. For a gate thickness of 6.5 nm, reduced boron dosage and rapid thermal processing solve the problem of boron penetration in the pure oxide case. However, when the film thickness is less than 6.5 nm, only a nitrided oxide film can solve the problem. From the results of EDX analysis in nitrided oxide films, it was found that nitrogen build-up at the interface is small and that a nitrogen concentration of only a few percent leads to complete suppression of boron penetration down to the 2 nm range of film thickness. Excellent characteristics in 2.6 nm nitrided oxide gate p-MOSFETs, free from boron penetration effects, were demonstrated.<<ETX>>

Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO/sub 2/ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-/spl mu/m and 0.06-/spl mu/m gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-/spl mu/m gate length pMOSFETs using 1.5-nm gate SiO/sub 2/ for the first time. The normal oscillations of the 1.5-nm gate SiO/sub 2/ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-/spl mu/m gate length CMOS in terms of high-frequency, high-speed operation.

Ultra-thin gate oxides-performance and reliability

Gate oxide thinning accompanied by the CMOS downsizing is expected to reach a direct-tunneling leakage current regime at the generations of 0.1 /spl mu/m and below. This has been regarded as one of the limiting factors of CMOS progress in terms of performance. Recently, the studies of the direct tunneling gate oxide have been carried out aggressively. In this paper, the results of these studies are reviewed and future prospects for the gate oxides are predicted.

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g/sub m/ of n-MOSFET with 40-nm epitaxial Si for 0.10-/spl mu/m gate length was 630 mS/mm at V/sub d/-1.5 V, and the drain current was 0.77 mA//spl mu/m. This g/sub m/ value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFETs are useful for future high-speed ULSI devices.