Tatsuya Ohguro

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFETs were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 /spl mu/m, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA//spl mu/m and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 /spl mu/m at room temperature. These are the highest values ever obtained with Si MOSFETs at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFETs if a high-capacitance gate insulator is used.

NiSi salicide technology for scaled CMOS

Salicide is one of the indispensable techniques for high-performance logic devices and its importance increases as the device dimensions become small towards sub-100 nm and hence, the source/drain sheet resistance becomes large. TiSi2 used popularly as the silicide material has been eventually replaced by CoSi2, because of its relatively stable nature during the salicide process. For sub-100-nm technology node, CoSi2 is expected to be further replaced by NiSi. NiSi has several advantages over TiSi2 and CoSi2 for the ultra-small CMOS process. They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance, (6) smaller contact resistance for both n- and p-Si, and (7) higher activation rate of B for SiGe poly gate electrode. In this paper, NiSi salicide technology is explained.

Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFETs was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFETs also operated at higher speed. >

Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films

The sheet resistance of TiSi/sub 2/-polycide (TiSi/sub 2/-polysilicon) lines increases as they are made narrower. This phenomenon has been investigated in detail. It is found that the relationship between sheet resistance and line width (W) is characterized by three distinct regions according to the value of W. The abrupt increase in sheet resistance observed in the region W/spl les/0.2 /spl mu/m cannot be explained in terms of the phase transition from C54 to C49, which we show to be the cause of the rising resistance at larger W. By adopting a new test pattern for sheet resistance measurements and using it in combination with TEM and EDX analysis we conclude that the cause of this abrupt increase is the presence of large inter-grain layers where silicide is very sparse. On the contrary, NiSi films have no such inter-grain layers, and good resistance values can be obtained even with 0.1 /spl mu/m lines. The NiSi process appears to be a suitable candidate to replace TiSi/sub 2/ in future deep-sub-micron high-speed CMOS devices. >

Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions

Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Even in the sub-50 nm region, short-channel effects-V/sub th/ shift and S-factor degradation-are suppressed very well. The impact ionization rate falls significantly as Vd falls below 1.5 V. It is found that, in the case of Vd less than 1.5 V, hot-carrier degradation is not a serious problem even in the sub-50 nm region.<<ETX>>

A 40 nm gate length n-MOSFET

Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as V/sub d/ falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if V/sub d/ is less than or equal to 1.5 V. >

Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 /spl mu/m/spl times/0.75 /spl mu/m, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n/sup +/ polysilicon gates subjected to RTA at 1050/spl deg/C for 20 s and furnace annealing at 850/spl deg/C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications.

HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics

Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs

Ultra-high performance n-MOSFETs were fabricated with a tunneling gate oxide 1.5 nm thick. It was found that these devices operate well when the gate length is around 0.1 /spl mu/m, because gate leakage current falls in proportion to the gate length and the drain current increases in inverse proportion. A very high drivability of 1.1 mAspl mu/m at 15 V was obtained, even in devices with a 0.14 pm gate length. A record high transconductance, 1,010 mS/mm at room temperature was also obtained in 0.09 /spl mu/m MOSFETs. Confirmation was obtained that hot-carrier reliability improves as the gate oxide thickness is reduced, even in the 1.5 nm case. High current drive at the low supply voltage of 0.5 V was also demonstrated. We made clear that very high performance is obtained in Si MOSFETs, if we can use a high capacitance gate insulator. In future devices, the tunnel gate oxide may be a good candidate for such a gate film, depending upon their applications.<<ETX>>

Future perspective and scaling down roadmap for RF CMOS

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.