Rakesh G. D. Jeyasingh

Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing

Brain-inspired computing is an emerging field, which aims to extend the capabilities of information technology beyond digital logic. A compact nanoscale device, emulating biological synapses, is needed as the building block for brain-like computational systems. Here, we report a new nanoscale electronic synapse based on technologically mature phase change materials employed in optical data storage and nonvolatile memory applications. We utilize continuous resistance transitions in phase change materials to mimic the analog nature of biological synapses, enabling the implementation of a synaptic learning rule. We demonstrate different forms of spike-timing-dependent plasticity using the same nanoscale synapse with picojoule level energy consumption.

An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation

The multilevel capability of metal oxide resistive switching memory was explored for the potential use as a single-element electronic synapse device. TiN/HfOx/AlOx/ Pt resistive switching cells were fabricated. Multilevel resistance states were obtained by varying the programming voltage amplitudes during the pulse cycling. The cell conductance could be continuously increased or decreased from cycle to cycle, and about 105 endurance cycles were obtained. Nominal energy consumption per operation is in the subpicojoule range with a maximum measured value of 6 pJ. This low energy consumption is attractive for the large-scale hardware implementation of neuromorphic computing and brain simulation. The property of gradual resistance change by pulse amplitudes was exploited to demonstrate the spike-timing-dependent plasticity learning rule, suggesting that metal oxide memory can potentially be used as an electronic synapse device for the emerging neuromorphic computation system.

An Ultra-Low Reset Current Cross-Point Phase Change Memory With Carbon Nanotube Electrodes

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 μA and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology.

Low-Energy Robust Neuromorphic Computation Using Synaptic Devices

Brain-inspired computing is an emerging field, which aims to reach brainlike performance in real-time processing of sensory data. The challenges that need to be addressed toward reaching such a computational system include building a compact massively parallel architecture with scalable interconnection devices, ultralow-power consumption, and robust neuromorphic computational schemes for implementation of learning in hardware. In this paper, we discuss programming strategies, material characteristics, and spike schemes, which enable implementation of symmetric and asymmetric synaptic plasticity with devices using phase-change materials. We demonstrate that energy consumption can be optimized by tuning the device operation regime and the spike scheme. Our simulations illustrate that a crossbar array consisting of synaptic devices and neurons can achieve hippocampus-like associative learning with symmetric synapses and sequence learning with asymmetric synapses. Pattern completion for patterns with 50% missing elements is achieved via associative learning with symmetric plasticity. Robustness of learning against input noise, variation in sensory data, and device resistance variation are investigated through simulations.

Energy efficient programming of nanoelectronic synaptic devices for large-scale implementation of associative and temporal sequence learning

A nanoscale, two-terminal device emulating plasticity and energy efficiency of biological synapses is a critical element for realizing brain-inspired computational systems and real-time brain simulators. In this work, we explore the use of phase change materials (PCM), widely used for memory applications, to build electronic synapses which implement synaptic plasticity with picojoule level energy consumption. Gradual switching characteristics and different spike schemes are discussed from implementation of synaptic plasticity and energy consumption perspectives. Our simulations demonstrate that a recurrent network of PCM synapses in a crossbar array can achieve brain-like associative and temporal sequence learning. Asymmetric plasticity is shown to transform temporal information into spatial information for sequence learning. Symmetric plasticity enables the storage and recall of certain patterns associatively by acting as a coincidence detector for neuronal activity.

Nanoscale phase change memory materials

Phase change memory materials store information through their reversible transitions between crystalline and amorphous states. For typical metal chalcogenide compounds, their phase transition properties directly impact critical memory characteristics and the manipulation of these is a major focus in the field. Here, we discuss recent work that explores the tuning of such properties by scaling the materials to nanoscale dimensions, including fabrication and synthetic strategies used to produce nanoscale phase change memory materials. The trends that emerge are relevant to understanding how such memory technologies will function as they scale to ever smaller dimensions and also suggest new approaches to designing materials for phase change applications. Finally, the challenges and opportunities raised by integrating nanoscale phase change materials into switching devices are discussed.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9× faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 × 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

Electronic and optical switching of solution-phase deposited SnSe2 phase change memory material

We report the use of chalcogenidometallate clusters as a solution-processable precursor to SnSe2 for phase change memory applications. This precursor is spin-coated onto substrates and then thermally decomposed into a crystalline SnSe2 film. Laser testing of our SnSe2 films indicate very fast recrystallization times of 20 ns. We also fabricate simple planar SnSe2 electronic switching devices that demonstrate switching between ON and OFF resistance states with resistance ratios varying from 7−76. The simple cell design resulted in poor cycling endurance. To demonstrate the precursor’s applicability to advanced via-geometry memory devices, we use the precursor to create void-free SnSe2 structures inside nanowells of ∼25 nm in diameter and ∼40 nm in depth.

AC conductance measurement and analysis of the conduction processes in HfOx based resistive switching memory

Impedance spectroscopy and AC conductance measurement were performed on HfOx based resistive switching memory. The fβ-like AC conductance is observable above a corner frequency for high resistance state (HRS). The index β is about 2 and is independent of DC bias or resistance value of different HRSs, suggesting that electron hopping between the nearest neighbor traps within the conductive filaments (CFs) is responsible for the measured AC conductance. The corner frequency shows up in a lower frequency regime for a higher HRS, indicating that a larger tunneling gap is formed between the electrode and the residual CFs.

Experimental demonstration of array-level learning with phase change synaptic devices

The computational performance of the biological brain has long attracted significant interest and has led to inspirations in operating principles, algorithms, and architectures for computing and signal processing. In this work, we focus on hardware implementation of brain-like learning in a brain-inspired architecture. We demonstrate, in hardware, that 2-D crossbar arrays of phase change synaptic devices can achieve associative learning and perform pattern recognition. Device and array-level studies using an experimental 10×10 array of phase change synaptic devices have shown that pattern recognition is robust against synaptic resistance variations and large variations can be tolerated by increasing the number of training iterations. Our measurements show that increase in initial variation from 9 % to 60 % causes required training iterations to increase from 1 to 11.