Zizhen Jiang

Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations.

Precise electrical manipulation of nanoscale defects such as vacancy nano-filaments is highly desired for the multi-level control of ReRAM. In this paper we present a systematic investigation on the pulse-train operation scheme for reliable multi-level control of conductive filament evolution. By applying the pulse-train scheme to a 3 bit per cell HfO2 ReRAM, the relative standard deviations of resistance levels are improved up to 80% compared to the single-pulse scheme. The observed exponential relationship between the saturated resistance and the pulse amplitude provides evidence for the gap-formation model of the filament-rupture process.

Verilog-A compact model for oxide-based resistive random access memory (RRAM)

We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.

Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model

Resistive switching random access memory (RRAM) is a leading candidate for next-generation nonvolatile and storage-class memories and monolithic integration of logic with memory interleaved in multiple layers. To meet the increasing need for device-circuit-system co-design and optimization for applications from digital memory systems to brain-inspired computing systems, a SPICE model of RRAM that can reproduce essential device physics in a circuit simulation environment is required. In this work, we develop an RRAM SPICE model that can capture all the essential device characteristics such as stochastic switching behaviors, multi-level cell, switching voltage variations, and resistance distributions. The model is verified and calibrated by a variety of electrical measurements on ~10 nm RRAMs. The model is applied to explore a wide range of applications including: 1) variation-aware design; 2) reliability-emphasized design; 3) speed-power assessment; 4) array architecture optimization; and 5) neuromorphic computing. This experimentally verified design tool not only enables system design that utilizes the complete suite of RRAM device features, but also provides solutions for system optimization that capitalize on device/circuit interaction.

Design and optimization methodology for 3D RRAM arrays

3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

1D Selection Device Using Carbon Nanotube FETs for High-Density Cross-Point Memory Arrays

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1-7 pJ per bit and has a high programming endurance of up to 106 cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <;1 μA are achieved.

A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

Ultra-Low Power Ni/HfO 2 /TiO x /TiN Resistive Random Access Memory With Sub-30-nA Reset Current

In this letter, we report ultra-low power (sub-30-nA reset current, Ireset) Ni/HfO2/TiOx/TiN RRAM devices that were fabricated with the rapid thermal oxidation of evaporated titanium. RRAM devices show forming-free, bipolar resistive switching behavior, low-resistive state (LRS) nonlinearity, good data retention, and stability. The resistive switching mechanism is mainly attributed to Schottky barrier modulation induced by O2- migration at the Ni/HfO2 interface. LRS/high-resistive state current conduction is controlled by Schottky emission/trap-controlled space-charge-limited current. The TiOx film is believed to provide a local high-density current for the device, confirmed by conductive atomic force microscope results.

Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.

Write disturb analyses on half-selected cells of cross-point RRAM arrays

Write disturb on half-selected (HS) cells is investigated through electrical measurements and large-scale array simulations. The experimental results collected from the individual devices under constant stress voltage and consecutive pulse operation are correlated with the HS cells in large-scale arrays based on a physics-based SPICE compact model. The impact of write/read disturb on the HS cells at different locations of the arrays is analyzed. Design guidelines for the optimized array size based on the experimental data and HSPICE simulations are presented: e.g., a 16 kb array can maintain its stored data pattern for 5×106 pulses and will have 164 false bits among half-selected cells after write disturb.

Atomically thin graphene plane electrode for 3D RRAM

3Å thick graphene edge was employed in the bit-cost scalable vertical RRAM structure to drastically reduce the total stack height to a single atomic layer. Two-layer 3D-stacked HfOx RRAM with graphene planar electrode (G-RRAM) is demonstrated in a 3D cross-point architecture with the edge of the graphene plane electrode serving as the bottom electrode of the RRAM. Exceptional memory window (>80×), low reset current (~20 μA), and suitable set/reset voltages (2 to 4 V) were achieved. Large memory window and low SET compliance ensures low reset current and low power consumption. Resistance components were separately measured to verify the role of graphene/oxide interface and the graphene sheet resistance. This work is a significant step toward extreme vertical scaling of 3D vertical stacked memory structures.