H.-U. Schreiber

A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >+or-100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2/sup 23/-1. A 0.9- mu m 12-GHz f/sub T/ silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W. >

A 8 Gb/s Si bipolar phase and frequency detector IC for clock extraction

A clock recovery (CR) approach based on a phase and frequency detector (PFD) has been implemented in a phase-and frequency-locked loop (PFLL). CR controlled by a PFD has been demonstrated up to 4 Gb/s. The Si bipolar PFD presented here operates up to 8 Gb/s, demonstrating its application in a PFLL. A block diagram is presented which shows that the input data stream samples the VCO signal and the delayed VCO signal (delay about 90 degrees ) in two sample-and-hold cells (S/H) that serve as phase detector (PD) and quadrature phase detector (QPD), respectively.<<ETX>>

A simple self-aligned Si bipolar transistor for high-speed integrated circuits

A self-aligned 12-GHz Si bipolar transistor was fabricated in a relatively poorly equipped laboratory. Emitter and base profiles were implanted and no polysilicon emitter was used. The base implantation was split into two parts, thus avoiding irreproducible items and perimeter effects. Circuit simulations indicated that bit rates of 10 Gb/s can be realized. For the simulations, double-staged emitter followers were used in both circuits, and bond pads and bond wires were taken into account. Further optimization of the transistor parameters and the transistor geometries in the circuits should yield still higher bit rates. >

A Si-bipolar technology for optical fiber transmission rates above 10 Gb/s

A multiplexer operating at up to 12 Gb/s has been demonstrated using a simple, but optimized, silicon bipolar technology with 2 mu m lithography. Using this simple but optimized technology, a 12 Gb/s multiplexer was implemented. Circuit simulations predict the increase of the bit rate up to at least 15 Gb/s by changing to the 1.5 mu m lithography. The results of experimental investigations and circuit simulations show that low-cost silicon-based bipolar circuits will be available for future optical-fiber transmission systems with data rates higher than 10 Gb/s. >

Electromigration in sputtered aluminum films

The electromigration behavior of sputtered aluminum films is discussed. Direct measurement of the aluminum drift velocity yielded a grain boundary activation energy of about 0.43 to 0.46 eV in the temperature range between 140 and 280°C. Time to failure and reliability were also tested and compared with electron-beam-evaporated aluminum, indicating a good quality for the sputtered films if sputter conditions are properly chosen.

Novel oxide planarization for integrated high-speed Si/SiGe heterojunction bipolar transistors

A straightforward oxide planarization for double mesa Si/SiGe heterojunction bipolar transistors (HBTs) is presented. The starting point is a bias-sputtered SiO/sub 2/ film covering a mesa with an auxiliary layer on top. The following planarization is performed only by wet chemical etching. A planarized multiplexer circuit resulted in bit rates up to 18 Gbit/s.

Measuring of low contact resistivities of CoSi/sub 2/ on shallow B-junctions

The active boron concentration, which affects contact resistivity, was profiled by stepwise four-point probing and Si reactive ion etching. The maximum concentration of 1.6/spl times/10/sup 20/ cm/sup -3/ remained constant up to a depth, which depends on the boron annealing temperature. This depth should be larger than the CoSi/sub 2/ penetration depth in Si. Conductance profiling of the silicide indicated an undesired layer on top of the CoSi/sub 2/. This upper layer influences contact resistivity. It is shown that the removal of this layer may reduce the contact resistivity down to 3 /spl Omega//spl mu/m/sup 2/.