J.N. Albers

Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications

A 1:4-demultiplexer IC meeting the essential requirements for lightwave communication systems has been designed based on a 21 GHz f/sub T/ 0.4 /spl mu/m Si bipolar process. The circuit provides features such as bit-rotation control, clock enable control, outputs aligned in time, and phase aligner for clock signals. It operates up to 14 Gb/s (14 GHz) with a phase margin of /spl ges/250/spl deg/. The power consumption is 2 W with a -4.5 V supply. 1:16-demultiplexer operation is demonstrated on the basis of 1:4-demultiplexer ICs at 10 Gb/s.

A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems

The 4:1-multiplexer reported here is based on a 21 GHz f/sub T/ 0.4 /spl mu/m silicon bipolar technology and operates up to 12 Gb/s. For facilitating system applications, the input signals are aligned in phase and retiming of the output signal is provided. A phase control circuit permits the choice of the optimum clock phase for the first and the second multiplexer stages; an internal delay line is not necessary. The 4:1-multiplexer consumes about 1.8 W with a single supply voltage of -4.5 V. >

Base contact resistance limits to lateral scaling of fully self-aligned double mesa SiGe-HBTs

Abstract A significant reduction of parasitic resistances and capacitances of the double mesa SiGe Heterojunction Bipolar Transistors (SiGe-HBT) was achieved by using self-aligned processing steps, such as planarization of transistor contacts, outside-spacer-technology for micromasking, contact implantation and low ohmic silicidation. This article presents and analyses the lateral optimization of the double mesa SiGe-HBT by on-wafer measurements and demonstrates lateral scaling limitation resulting from the increasing base metal-semiconductor contact resistance. The increase of the more important base contact resistance is proven by two-dimensional contact simulation. This is shown experimentally by using a fully self-aligned double mesa SiGe-HBT transistor which combines the advantages of superior high frequency characteristics with a simple and low cost fabrication procedure being used mainly in compound semiconductor technology.

Monolithic retimed receiver array with dynamic reference level comparator for 4/spl times/2 Gb/s synchronous optical data link

A DC-coupled 4-channel synchronous optical receiver with 8-Gb/s aggregate throughput has been designed using a monolithic silicon bipolar IC and an InGaAs p-i-n photodiode array. Each channel employs a positive feedback structure to dynamically generate threshold voltage in the decision which enables single-ended-to-differential signal conversion without coupling capacitors or reference voltage subcircuits. Power dissipation is 865 mW at -5.5 V supply voltage.

Modified feedback ECL gate for Gb/s applications

This paper introduces a modification of the feedback emitter-coupled logic (FECL) gate that makes it suitable for Gb/s applications. The circuit can be used as a single-ended-to-differential signal converter without the need for an external reference voltage and finds application in digital optical links in which data is typically transmitted single ended. The gate is compared with FECL and ECL gates, and its application to realize logic functions is discussed. A 6-Gb/s series gated decision circuit and a 2-Gbaud/s four-channel optical receiver array employing modified FECL gates are also described.