U. Langmann

A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >+or-100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2/sup 23/-1. A 0.9- mu m 12-GHz f/sub T/ silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W. >

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

A 2nd-order continuous-time quadrature bandpass /spl Sigma//spl Delta/ modulator with 1 MHz IF clocked at 100 MHz digitizes I and Q inputs with SNDR of 56.2 dB for 1 MHz bandwidth inputs. The 0.65 /spl mu/m BiCMOS chip consumes 21.8 mW at 2.7 V, and operates with a clock-frequency range of 25-100 MHz.

A 10 Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver

The use of high bit rates for TDM transmissions on long haul fiber links is not only limited by the speed of electronic components but also by problems like fiber dispersion, polarization mode dispersion and fiber nonlinearities, especially if an installed standard fiber is used. An approach to alleviate these problems is the use of electronic signal-processing functions and advanced modulation schemes. This single chip eye opening monitor (EOM) is for use as part of such a signal processing unit. Apart from the data signal, a regenerated clock of arbitrary phase is needed to generate a dc output voltage proportional to the horizontal eye opening with a response time of <1 ms. The IC, in 50 GHz-f/sub T/ SiGe bipolar technology, covers bit rates from 2 to 12.5 Gb/s and dissipates 4.95 W from -5 V.

An 8 GHz silicon bipolar clock-recovery and data-regenerator IC

This contribution shows that a monolithic integrated silicon bipolar circuit can provide phase and frequency locked loop (PFLL) based clock recovery and data regeneration up to 8Gb/s. Moreover, phase and frequency detector (PFD) operation up to 15Gb/s (with an external VCO) is demonstrated. Owing to the wide tuning range of the quadrature VCO, the circuit lends itself to operation over a wide range of bit rates. Other applications of the quadrature VCO, e.g. as a synthesizer, are possible. As shown by circuit simulations, the operating frequency can be extended beyond 1OGHz, if a small unbalance between both ring oscillator stages is eliminated by minor design changes. >

A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC

This article gives a detailed presentation of an all-npn silicon bipolar Track&Hold IC for 10-b operation up to 1 GSample/s under full Nyquist conditions. Circuit techniques were implemented to reduce the pedestal, hold-mode feedthrough, and droop errors. An experimental Track&Hold IC was fabricated in a 25-GHz-f/sub T/, 0.4-/spl mu/m-emitter-width single-poly base silicon bipolar production technology. Each of the Track&Hold circuits in this IC consists of 103 active devices and consumes 490 mW from a single supply voltage, including bandgap-references and input buffers.

A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output

This paper describes a 60GHz LNA, implemented in a 65nm digital CMOS technology, that has a single-ended input and a differenntial output. At 59.3GHz, the LNA achieves a maximum voltage gain of 22.3dB (power gain of 19.3dB). The input matching is better than -lOdB over the entire 3dB bandwidth from 55.8GHz to 63.5GHz. The LNA has a minimum measured NF of 6.1dB, an output compression point of +2.7dBm and draws 29mA from a 1.2V supply.

A 90GHz 65nm CMOS Injection-Locked Frequency Divider

Two injection-locked 2:1 frequency dividers for automotive radar applications achieve locking ranges from 82 to 94.1 GHz and from 34.3 to 42.1 GHz and consume 4mW and 8.4mW, respectively. The cascade of the two dividers can be locked from 79.7 to 81.6GHz. The 1mm2 chip is implemented in a 65nm CMOS process.

Multi-Gb/s silicon bipolar clock recovery IC

A novel clock recovery IC for optical fiber communication systems with data rates up to several Gb/s is presented. It combines nonlinear signal preprocessing directly with a regenerative frequency divider scheme and an external filter in the divider loop. Hence, the center frequency of the filter and the working frequency of the amplifier are halved. The extracted clock frequency corresponds to half the bit rate, as required for many clocked circuit components within fiber optic lines. Two versions of the same IC design, scheduled for two bit rate ranges between 0.3-4 Gb/s, are realized with a conventional Si bipolar process. Clock recovery is demonstrated at 2.2 and 3.52 Gb/s, using both cavity and surface acoustic wave (SAW) filters. >

A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator

A 10 Gb/s clock and data recovery (CDR) circuit for use in multi-channel applications is presented. The module comprises a binary phase detector, an analog phase interpolator, and a 1:4 demultiplexer. The prototype macro fabricated in a 0.11 /spl mu/m CMOS technology consumes 220 mW. The active area is about 0.25/spl times/1.4 mm/sup 2/. The CDR fulfills the jitter tolerance requirements set by SDH/SONET with the test being based on a BER of 10/sup -12/ and a PRBS of 2/sup 23/-1.