H. V. Jagadish

The RightPages image-based electronic library for alerting and browsing

The RightPages electronic library prototype system, which gives users full online library services, is described. The prototype takes advantage of fast hardware, multimedia workstations, and broadband networks to process scientific and technical journals for users and to offer a service that: alerts them to the arrival of new journal articles matching their interest profiles; lets them immediately examine images of pages in the alerted articles and browse through other articles in the database; and enables them to order paper copies of any articles in the database. The system runs on a local area network that connects one or more scanning stations, a centralized document database server and multiple user stations running X Windows servers. The RightPages interface runs as an X Windows application on Sun workstations or X terminals. The systems image and document processing, including noise reduction, document layout analysis, text processing, and display processing are discussed.<<ETX>>

Array architectures for iterative algorithms

Regular mesh-connected arrays are shown to be isomorphic to a class of so-called regular iterative algorithms. For a wide variety of problems it is shown how to obtain appropriate iterative algorithms and then how to translate these algorithms into arrays in a systematic fashion. Several systolic arrays presented in the literature are shown to be specific cases of the variety of architectures that can be derived by the techniques presented here. These include arrays for Fourier Transform, Matrix Multiplication, and Sorting.

Towards a Gigabit IP Router

In this paper we illustrate the application of SWIMs Active Storage Element (ASE) module in constructing high performance IP routers. The logic associated with each ASE is a wide-instruction-word micro-programmable engine, that has been specially designed to efficiently perform operations such as pointer dereferencing, memory indirection, bounds checking, and so forth. This makes it well suited to performing operations such as parsing of the IP header, routing table lookup, checksum computation and exception processing. Our results show that a single ASE running at 20 MHz can process 400,000 packets per second: well over that required to sustain a gigabit router. Multiple ASEs can be used in parallel to achieve even higher processing rates.

An object model for image recognition

The use of object-oriented database principles to help model an image for computer vision, specifically, for line-image analysis, is described. The resulting representation, called thin line code (TLC), is general across known applications and extensible to new applications. TLCs advantages, and also some difficulties it has in strictly adhering to traditional notions of object orientation, are addressed. A review of relevant aspects of object modeling is included.<<ETX>>

A family of new efficient arrays for matrix multiplication

The authors present a regular iterative algorithm for matrix multiplication and show that several well-known matrix multiplication arrays are directly obtained from it, differing only in the choice of iteration vector. They then present a regular iterative algorithm for matrix multiplication using the S. Winograd method (1968) and show in detail how to derive one array from this algorithmic description. Other arrays in the same family can similarly be obtained for different choices of the iteration space. The new arrays compute the product of two matrices faster than available conventional arrays and use a smaller number of processor cells. >

Obtaining schedules for digital systems

A systematic technique is presented to derive correct schedules for a synchronous digital system, given a signal flow graph for an algorithm. It is also shown how to use this technique to derive designs that are optimal in having the lowest latency, the highest throughput, or the smallest number of registers. The same technique can also be used to verify digital systems that have already been designed. >

An intelligent memory system

SWIM(Structured Wafer-Scale Intelligent Memory) is a high bandwidth, multi-ported, disk-sized memory system capable of storing, maintaining, and manipulating data structures within it, independent of the main processing units. Up to thousands of active storage elements, each element having some storage and some associated processing logic, function independently or in groups to implement userdefined objects. SWIM increases memory functionality to better balance the time spent in moving data with that involved in actually manipulating it. Just as one may associate a cache with each processor, each memory module has processing logic associated with it. Such logic decreases the processormemory bandwidth requirements, improves memory utilization, scales better in a multiprocessor, and yields a faster response from memory. The faster response results from proximity, a specialized micro architecture and parallelism.

The Design of a Back-end Object Management System

We describe the architecture and design of a back-end object manager, designed as an “active memory” system on a plugin board for a standard workstation (or personal computer). We show how, with minimal modification to existing code, it is possible to achieve significant performance improvement for the execution of data-intensive methods on objects, simply by using our back-end object manager.

An intelligent memory transaction engine

In this paper, we describe the structure and utilization of a high bandwidth, multi-ported, disk-sized memory system capable of storing, maintaining, and manipulating persistent shared data within it, independent of any external processing units. Up to thousands of active storage elements, each element having some storage and some associated processing logic, function independently or in groups to implement user-defined objects and data structures. Hundreds of transactions can concurrently be processed by mutually exclusive sets of elements. A fast response time is obtained due to the proximity of the processing with the memory, a specialized micro-architecture, and parallelism.

The trap as a control flow mechanism

In this paper we show how traditional hardware trap handlers can be generalized into an efficient vehicle for conditional branches. These ideas are being used in a VLSI processor under design. Conditional branches are often a major bottleneck in scheduling microinstructions on a horizontally microcoded machine. Several tests and conditional branches are frequently ready for scheduling simultaneously, but only one test and branch is possible in a given cycle. The trap facility is traditionally treated as an interrupt scheme for the notification of exceptional conditions. In this paper we study how the role of the trap mechanism may be expanded to include the parallel evaluation of arbitrary user-specified tests, and the concomitant performance benefits.