Scott C. Knauer

Digitally adjustable resistors in CMOS for high-performance applications

Methods by which CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits are described. Since digital signals are the only inputs to these circuits, on-chip DC power dissipation can be reduced, the circuit can be made more robust, and the impedance of the circuit can be adjusted by manipulating the input digital information. A design of a CMOS series terminated line driver is discussed, and the utilization of the controlled impedance in terminating transmission lines on-chip, constant delay lines, and controlled di/dt output buffers is discussed. >

A codec for HDTV

A high-quality digital video codec has been developed for the Zenith/AT&T HDTV system. It adaptively selects between two transmission modes with differing rates and robustness. The codec works on an image progressively scanned with 1575 scan lines every 1/30th of a second and achieves a compression ratio of approximately 50 to 1. The high compression ratio facilitates robust transmission of the compressed HDTV signal within an NTSC taboo channel. Transparent image quality is achieved using motion compensated transform coding coupled with a perceptual criterion to determine the quantization accuracy required for each transform coefficient. The codec has been designed to minimize complexity and memory in the receiver. >

An I/O CMOS buffer set for silicon multichip module's (MCM)

A set of I/O CMOS buffers for MCM is described. When simulation results of the MCM buffers are compared against conventional standard cell CMOS buffers, several advantages emerge. The results indicate that the new buffers dissipate 5 times less power, reduce propagation delay from chip core to another core from 3-6 nsec, and increase the frequency of operation by 2.5 times when compared to conventional CMOS buffers. Actual measurements between these buffers confirm these simulation results.<<ETX>>

Architecture and implementation of ICs for a DSC-HDTV video decoder system

The architecture and implementation of the very-large-scale integrated (VLSI) video decoder subsystems in digital spectrum compatible high-definition television (DSC-HDTV) systems are discussed. The CMOS deformatter IC, which converts formatted data back to motion vectors, DCT coefficients, and coding parameters, and the motion compensator and inverse discrete transform IC, which reconstructs frames from the deformatter-decoded coefficients, are described.<<ETX>>

A High Quality Digital HDTV Codec

A digital video codec has been developed for the Zenith/AT&T HDTV (high-definition TV) system for terrestrial broadcast over NTSC taboo channels. The codec works on an image progressively scanned with 1575 scan lines every 1/30th of a second and achieves a compression ratio of approximately 50 to 1. The transparent image quality is achieved using motion-compensated transform coding coupled with a perceptual criterion to determine the quantization accuracy required for each transform coefficient. The combination of a sophisticated encoded video format and advanced bit error protection techniques results in a highly robust reception and decoding of the compressed video signal. >

An intelligent memory system

SWIM(Structured Wafer-Scale Intelligent Memory) is a high bandwidth, multi-ported, disk-sized memory system capable of storing, maintaining, and manipulating data structures within it, independent of the main processing units. Up to thousands of active storage elements, each element having some storage and some associated processing logic, function independently or in groups to implement userdefined objects. SWIM increases memory functionality to better balance the time spent in moving data with that involved in actually manipulating it. Just as one may associate a cache with each processor, each memory module has processing logic associated with it. Such logic decreases the processormemory bandwidth requirements, improves memory utilization, scales better in a multiprocessor, and yields a faster response from memory. The faster response results from proximity, a specialized micro architecture and parallelism.

Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs

Compared to conventional packaging, multichip modules have significantly reduced capacitive loading in their interconnections. The authors present experimental results showing the performance of I/O buffers specially designed to operate in this environment, evaluated in several different silicon-on-silicon test modules.<<ETX>>

A high quality digital HDTV codec

A digital video codec has been developed for the Zenith/AT&T HDTV system for terrestrial broadcast over NTSC taboo channels. The codec works on an image progressively scanned with 1575 scan lines every 1/30th of a second and achieves a compression ratio of approximately 50 to 1. The transparent image quality is achieved using motion compensated transform coding coupled with a perceptual criterion to determine the quantization accuracy required for each transform coefficient. The combination of a sophisticated encoded video format and advanced bit error protection techniques results in a highly robust reception and decoding of the compression video signal.<<ETX>>

An intelligent memory transaction engine

In this paper, we describe the structure and utilization of a high bandwidth, multi-ported, disk-sized memory system capable of storing, maintaining, and manipulating persistent shared data within it, independent of any external processing units. Up to thousands of active storage elements, each element having some storage and some associated processing logic, function independently or in groups to implement user-defined objects and data structures. Hundreds of transactions can concurrently be processed by mutually exclusive sets of elements. A fast response time is obtained due to the proximity of the processing with the memory, a specialized micro-architecture, and parallelism.