Ha-Duong Ngo

Tuning Piezo ion channels to detect molecular-scale movements relevant for fine touch

In sensory neurons, mechanotransduction is sensitive, fast and requires mechanosensitive ion channels. Here we develop a new method to directly monitor mechanotransduction at defined regions of the cell-substrate interface. We show that molecular-scale (~13 nm) displacements are sufficient to gate mechanosensitive currents in mouse touch receptors. Using neurons from knockout mice, we show that displacement thresholds increase by one order of magnitude in the absence of stomatin-like protein 3 (STOML3). Piezo1 is the founding member of a class of mammalian stretch-activated ion channels, and we show that STOML3, but not other stomatin-domain proteins, brings the activation threshold for Piezo1 and Piezo2 currents down to ~10 nm. Structure–function experiments localize the Piezo modulatory activity of STOML3 to the stomatin domain, and higher-order scaffolds are a prerequisite for function. STOML3 is the first potent modulator of Piezo channels that tunes the sensitivity of mechanically gated channels to detect molecular-scale stimuli relevant for fine touch.

Design and simulation of ultra high sensitive piezoresistive MEMS sensor with structured membrane for low pressure applications

In order to increase the sensitivity of a piezoresistive pressure sensor, the membrane needs to be very thin or very large to achieve good results. But there is a trade-off between stability, linearity and sensitivity. The thinner the membrane, the more instable is the sensor structure. The original sensor developed for wall pressure measurement has a membrane thickness of 4 µm [1][2]. The herein presented idea is to use partly-structured thicker membranes to improve the sensor performance. In this paper we show the optimization of the new sensor structure by using DoE (Design of Experiment) and FEA with ANSYS software. Due to the optimized membrane structure, the sensor sensitivity could be increased up to 300 % in comparison to sensors using unstructured silicon membranes.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices

Through-silicon-via (TSV) interconnects using the “via-last” approach are successfully applied for wafer-level packaging of complementary metal-oxide-semiconductor (CMOS) image sensors. Standard materials and processes are applied for redistribution on the backside of the devices, which is enabled by the use of plasma etched vias with tapered sidewalls. With this, high reliability for the packaged devices are achieved on component and board level. Based on the high uniformity for the via geometry in respect to the dimension of top opening, bottom opening, and sidewall angle, we discuss the coverage of those redistribution polymers and photo resists as the bases for high performance and high yield of the mature wafer-level packaging process for optical and M(O)EMS devices.

Liquid-free, piezoresistive, SOI-based pressure sensor for high temperature measurements up to 400 °C

In this paper a novel liquid-free, piezoresistive pressure sensor on SOI-basis (Silicon On Insulator) for high temperature applications is presented. The sensor is capable of measuring pressures at temperature up to 400 °C (constant load) with an accuracy of 0.25 % FSO (Full Scale Output). Media separation is realized using a steel membrane. A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the centerboss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by DRIE (Deep Reactive Ion Etching or Bosch Process). Novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used. Thereby, avoiding chip movement, optimal push rod load transmission is ensured. The housing consists of different sections optimized for compensation of CTE (Coefficient of Thermal Expansion) mismatches. Utilizing this novel packaging scheme and combining different housing materials, temperature, wear, and long term fatigue stability are assured.

Copper filling of TSVs for interposer applications

For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as their quantity on the wafer have a severe influence on the electrochemical process parameters, in particular on the current process time profile. So the electrochemical deposition (ECD) current was investigated in dependence of the filling progress, the height-to-depth aspect ratio, and the quantity of high aspect ratio vias on the wafer. The same applies to the number of plating steps at constant current, their length, and the total process time. Valuable insights for the design of via filing recipes could be deduce thereof.

Packaging of MEMS/MOEMS and nanodevices: reliability, testing, and characterization aspects

The last decade witnessed an explosive growth in research and development efforts devoted to MEMS devices and packaging. The successfully developed MEMS devices are, for example inkjet, pressure sensors, silicon microphones, accelerometers, gyroscopes, MOEMS, micro fuel cells and emerging MEMS. For the next decade, MEMS/MOEMS and nanodevice based products will penetrate into IT, telecommunications, automotive, defense, life sciences, medical and implantable applications. Forecasts say the MEMS market to be

A WSi–WSiN–Pt Metallization Scheme for Silicon Carbide-Based High Temperature Microsystems

14 billion by 2012. The packaging cost of MEMS/MOEMS products in general is about 70 percent. Unlike todays electronics IC packaging, their packaging are custom-built and difficult due to the moving structural elements. In order for the moving elements of a MEMS device to move effectively in a well-controlled atmosphere, hermetic sealing of the MEMS device in a cap is necessary. For some MEMS devices, such as resonators and gyroscopes, vacuum packaging is required. Usually, the cap is processed at the wafer level, and thus MEMS packaging is truly a wafer level packaging. In terms of MEMS/MOEMS and nanodevice packaging, there are still many critical issues need to be addressed due to the increasing integration density supported by 3D heterogeneous integration of multi-physic components/layers consisting of photonics, electronics, rf, plasmonics, and wireless. The infrastructure of MEMS/MOEMS and nanodevices and their packaging is not well established yet. Generic packaging platform technologies are not available. Some of critical issues have been studied intensively in the last years. In this paper we will discuss about processes, reliability, testing and characterization of MEMS/MOEMS and nanodevice packaging.

Zero Bias Anomaly in an Individual Suspended Electrospun Nanofiber

In this paper, we present and discuss our new WSi–WSiN–Pt metallization scheme for SiC-based microsystems for applications in harsh environments. Stoichiometric material WSi was selected as contact material for SiC. The diffusion barrier material WSiN was deposited from the same target as the contact material in order to limit the number of different chemical elements in the scheme. Our scheme was kept as simple as possible regarding the number of layers and chemical elements. Our scheme shows very good long-term stability and suitability for SiC-based microsystems. The experimental evaluation concept used here includes a combination of physical, electrical, and mechanical analysis techniques. This combined advance is necessary since modern physical analysis techniques still offer only limited sensitivity for detecting minimal changes in the metallization scheme.

Mechanical Properties of Individual Composite Poly(methyl-methacrylate) - Multiwalled Carbon Nanotubes Nanofibers

We report observing a double broad Kondo-like zero bias conductance peak at low temperatures in individual suspended electrospun nanofibers Poly(methyl methacrylate)- multiwalled carbon nanotubes. This anomalous behavior is suppressed at higher temperatures. We attribute this to the existence of correlated double impurity system inside the nanofiber. From the results we calculate a Kondo-like temperature for the nanofiber to be ~31.7-34K.