Klaus-Dieter Lang

High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes

Through-silicon vias (TSVs) in low, medium and high resistivity silicon for 3-D chip integration and interposers are modeled and thoroughly characterized from 100 MHz to 130 GHz, considering the slow-wave, dielectric quasi-TEM and skin-effect modes. The frequency ranges of these modes and their transitions are predicted using resistivity-frequency domain charts. The impact of the modes on signal integrity is quantified, and three coaxial TSV configurations are proposed to minimize this impact. Finally, conventional expressions for calculating the per-unit-length circuit parameters of transmission lines are extended and used to analytically capture the frequency dependent behavior of TSVs, considering the impact of the mixed dielectric (silicon dioxide-silicon-silicon dioxide) around the TSVs. Excellent correlation is obtained between the analytical calculations using the extended expressions and electromagnetic field simulations up to 130 GHz. These extended expressions can be implemented directly in electronic design automation tools to facilitate performance evaluation of TSVs, prior to system design.

Analytical, Numerical-, and Measurement–Based Methods for Extracting the Electrical Parameters of Through Silicon Vias (TSVs)

In this paper, analytical, numerical-, and measurement-based methods for extracting the resistance, inductance, capacitance, and conductance of through silicon vias (TSVs) are classified, quantified, and compared from 100 MHz to 100 GHz. An in-depth analysis of the assumptions behind these methods is made, from which their limits of accuracy/validity are defined. Based on this, the most reliable methods within the studied frequency range are proposed. The TSVs are designed, fabricated, and measured. Very good correlation is obtained between electrical parameters of the TSVs extracted from the measurements and electromagnetic field simulations.

Data availability and the need for research to localize, quantify and recycle critical metals in information technology, telecommunication and consumer equipment

The supply of critical metals like gallium, germanium, indium and rare earths elements (REE) is of technological, economic and strategic relevance in the manufacturing of electrical and electronic equipment (EEE). Recycling is one of the key strategies to secure the long-term supply of these metals. The dissipation of the metals related to the low concentrations in the products and to the configuration of the life cycle (short use time, insufficient collection, treatment focusing on the recovery of other materials) creates challenges to achieve efficient recycling. This article assesses the available data and sets priorities for further research aimed at developing solutions to improve the recycling of seven critical metals or metal families (antimony, cobalt, gallium, germanium, indium, REE and tantalum). Twenty-six metal applications were identified for those six metals and the REE family. The criteria used for the assessment are (i) the metal criticality related to strategic and economic issues; (ii) the share of the worldwide mine or refinery production going to EEE manufacturing; (iii) rough estimates of the concentration and the content of the metals in the products; (iv) the accuracy of the data already available; and (v) the occurrence of the application in specific WEEE groups. Eight applications were classified as relevant for further research, including the use of antimony as a flame retardant, gallium and germanium in integrated circuits, rare earths in phosphors and permanent magnets, cobalt in batteries, tantalum capacitors and indium as an indium–tin-oxide transparent conductive layer in flat displays.

Polyimide based temporary wafer bonding technology for high temperature compliant TSV backside processing and thin device handling

Temporary wafer bonding for thin wafer processing is one of the key technologies of 3D system integration. In this context we introduce the polyimide material HD3007 which is suitable for temporary bonding of silicon wafers to carrier wafers by using a thermo compression process. Coating and bonding processes for 200 mm and 150 mm wafers with and without topography as well as two de-bonding concepts which are based on laser assisted and solvent assisted release processes are presented. Based on tests with temporary bonded 200 mm wafers, we found a very high compatibility of the bonded compound wafers with standard WLP process equipment and work flows suitable for backside processing of “via first” TSV wafers. Processes like silicon back grinding to a remaining thickness of 60 μm, dry etching, wet etching, CMP, PVD, spin coating of resists and polymers, lithography, electro plating and polymer curing were evaluated and are described in detail. Even at high temperatures up to 300°C and vacuum levels up to 10-4 mbar, the temporary bond layer was stable and no delamination occurred. 60 μm thin wafers could be processed and de-bonded without any problems using both release methods. De-bonding times of less than a couple minutes can be realized with laser assisted de-bonding and several minutes with a solvent based release. Compared to glues of other temporary handling systems, the proposed material offers the highest temperature budget for thin wafer backside processing as well as fast and easy de-bonding at room temperature.

Through mold vias for stacking of mold embedded packages

The constant drive towards further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8” to 12”. Future developments will deal with panel sizes up to 470 × 370 mm². The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components — whichever no matter which shape they are: a compression molded wafer or a larger rectangular area of a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating — all of them making use of standard PCB processes. Thus, through vias which are standard features in PCB manufacturing and can be also integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. Vias were drilled by laser or mechanically after RCC lamination and were metalized together with the vias for chip interconnection. Within this study different liquid and granular molding compounds have been intensively evaluated on their processability. Via drilling process by laser and mechanical drilling is systematically developed and analyzed with focus on via diameter, pitch, mold thickness and molding compound composition and here especially on filler particle sizes and distribution. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Finally, a technology demonstrator is described consisting of two BGAs stacked on each other and mounted on a base substrate enabling the electrical test of a daisy chain structure through the stacked module, allowing the evaluation of the technology and the applied processes.

Modeling, Quantification, and Reduction of the Impact of Uncontrolled Return Currents of Vias Transiting Multilayered Packages and Boards

The returning displacement currents of vias transiting multilayered stack-ups in electronic packages and boards excite parasitic transverse electromagnetic modes in power-ground plane pairs, causing them to behave as parallel-plate waveguides. These waves may cause significant coupling in the power-ground cavity, leading to electromagnetic reliability (EMR) issues such as simultaneous switching noise coupling, high insertion loss degradation of signal vias, and stray radiation from the periphery/edges of the package/board. In this contribution, we model and quantify EMR problems caused by uncontrolled return currents of signal vias in conventional multilayer stack-ups. Traditional methods used to minimize these problems, and their limitations are discussed. We propose a low-cost layer stack-up, which overcomes most of the limitations of conventional stack-ups by providing well-defined return-current paths for microstrip-to-microstrip via transitions. Test samples of the proposed configuration are designed, fabricated, and measured. Very good correlation is obtained between measurement and simulation. Finally, a circuit model for the microstrip-to-microstrip via transition, considering the return-current paths, is developed and the circuit parameters are analytically calculated. Conventional closed-form expressions used for the extraction of these parameters, particularly the via capacitance, are extended and modified.

Predicting the Shear Strength of a Wire Bond Using Laser Vibration Measurements

Wedge/wedge bonding with AlSi-1 wire on semiconductor chips with aluminum metallization has been investigated. The scope of the article is the modeling of the wedge bond. The description of the bonding process by a physical model shall predict the change of bond quality, depending on a change in bonding parameters. The physical model is based on measurements of the vibration amplitude, induced into the assembly by the ultrasonic (US) power. The model is derived by measurements of the shear strength for various bond times. By fitting the calculation to the measurements, details of the bonding process can be clarified.. By using the model shear force can be calculated by estimation of the deformation of the wire material, the amplitude of the tool, sigma and the transversal force during bonding

From wafer level to panel level mold embedding

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. Mold embedding is currently done on wafer level, typically with diameters of 8“ to 12”, for future process optimization, PCB technologies offer the potential of real large areas up to 610 × 457 mm2. For mold embedding as e.g. for fan-out wafer level packaging compression molding equipment is used in combination with liquid, granular or sheet epoxy molding compounds, with the boundary condition, that mold processes do need a product specific tool (with defined diameter & thickness). Within this paper the potential of tool-less lamination processes, a standard in PCB manufacturing, is evaluated. Lamination is done in panel format using well-known molding compounds from wafer level compression molding. To evaluate the potential of todays encapsulants for large area embedding processes, different liquid, granular and sheet molding compounds have been intensively evaluated on their processability, on process & material induced die shift and on resulting warpage - all on panel level. Acting as an interconnection layer, PCB based redistribution technologies using lamination of resin coated copper (RCC) films are used. Within the paper, different RCC materials are introduced and discussed concerning their reliability potential based on the available layer thicknesses and thermo-mechanical material properties. The feasibility of the proposed technologies is demonstrated using a two chip package. Dies are embedded in panel size by lamination technologies. Subsequently the wiring is done by lamination of an RCC film over the embedded components and on the panel backside for double sided redistribution. In a process flow also similar to conventional PCB manufacturing μvias to the die pads and through mold vias are drilled using a UV laser and are metalized by Cu-electroplating in one step. This way dies are connected to the front copper layer as well as front to backside of the panel. Conductor lines and pads are formed by Cu etching. Finally, a solder mask and a solderable surface finish are applied. If solder depots are necessary, e.g. for BGA packages, those can be applied by solder balling equipment - either by printing or by preform attach. In summary this paper describes the potential to move from wafer level to panel level mold embedding technology in combination with PCB based redistribution processes. The technology described offers a cost effective packaging solution for e.g. single chip packages as well as for future sensor/ASIC systems or processor/memory stacks in volume production.

Through mold via technology for multi-sensor stacking

With the increasing market of handheld electronics e.g. smartphones and tablet PCs also an increasing demand for highly miniaturized multi-sensor packages shows up. One application scenario here would be an electronic compass allowing indoor navigation in complex buildings with a smartphone. These applications of highly miniaturized heterogeneous system integration lead to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding is one major packaging trend in this area. This paper describes the use of advanced molding techniques for multi-chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a technological approach that has been developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale. Embedding area today is typically in the size range of 8” to 12” in diameter, while future developments will deal with panel sizes up to 470 × 370 mm². The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components — whichever no matter which shape they are: a compression molded wafer or a larger rectangular area or a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating — all of them making use of standard PCB processes. Also through vias for z-axis interconnection, a standard features in PCB manufacturing, can be integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. These vias were laser drilled after RCC lamination and were metalized together with the vias for chip interconnection. Reliability of the manufactured through mold vias with different via diameters and pitches was evaluated by moisture sensitivity level [MSL] testing, temperature cycling and humidity storage and test vehicles were analyzed both non-destructively and destructively. Results show high reliability potential of the introduced through mold via technology as samples have passed MSL 1 and more than 3000 temperature cycles and 3000 hour humidity storage without any electrical failure. The embedding and stacking technology is demonstrated for a functional two chip package consisting of an acceleration sensor and an ASIC. On top of this package a second wafer level embedded package is assembled containing a pressure sensor and an ASIC. Both WL packages are connected by the through mold vias and soldered to a base substrate. Concluding, within this paper on mold embedded SiPs both is shown — the development of TMVs, an advanced and low cost 3D packaging feature and demonstration of use of this feature for the assembly of a functional 3D multi-sensor system, illustrating the miniaturization potential of 3D system integration.

A lead free joining technology for high temperature interconnects using Transient Liquid Phase Soldering (TLPS)

This Paper reports an emerging lead-free joining technology for high temperature application, which can be used for operating temperatures above 200 °C. It is called: “Transient Liquid Phase Soldering (TLPS)”. The TLPS paste used contains a tin-copper powder mixture and is almost completely transformed into Cu6Sn5 and Cu3Sn intermetallic phases after soldering. Due to the reaction between the liquid tin and the copper powder a skeleton of intermetallic phases are formed immediately during soldering and prevents the paste from collapsing so that a lot of voids remain in the solder line. The challenge for this investigation was to understand the mechanism of the skeleton formation, describe them in detail and find possibilities to avoid the skeleton formation. In this paper a new TLPS paste and two processes are described as a means to manufacture an almost void-less joint. Furthermore, a model was developed that describes the TLPS process in detail. The activation of the TLPS joint is crucial and will be described. Temperature cycling results, failure mechanisms and conclusions to increase the lifetime as well as reliability of such TLPS interconnects will be presented in this paper.