Hae-Moon Seo

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode

Relationship between ADC performance and requirements of digital-IF receiver for WCDMA base-station

The recent rapid development of digital wireless systems has led to the need for multistandard, multichannel radiofrequency (RF) transceivers. The paper presents the relationship between the performance of a bandpass-sampling analog-to-digital converter (ADC) and the requirements of a digital intermediate-frequency receiver for a wideband code-division multiple-access (WCDMA) base-station. As such, the ADC signal-to-noise ratio (SNR), the derivation of the receiver sensitivity using the SNR/spurious free dynamic range (SFDR) of the ADC, the effect of the ADC clock jitter and receiver linearity, plus the relationship between the receiver IF and the ADC sampling frequency are all analyzed. As a result, when a WCDMA base-station receiver has a data rate of 12.2 kbps, bit error rate (BER) of 0.001, and channel index, k, of 5 (sampling frequency of 122.88 MHz and IF of 92.16 MHz), the performance of a bandpass-sampling ADC was analytically determined to require a resolution of 14 bits or more, SNR of 66.6 dB or more, SFDR of 86.5 dBc or more, and total jitter of 0.2 ps or less, including internal ADC jitters and clock jitters.

Architectural Design of Home Energy Saving System Based on Realtime Energy-Awareness

Recently, a global market related to energy efficiency and energy saving technologies is being extended rapidly with the growth of a matter of primary concern about extreme climate change. Especially, in the home network environments where only its functional aspects have been focused on without considering energy consumption, it is urgent to develop new energy-efficient technologies specialized in the home network environments. In this paper, architecture of home energy saving system (HESS) based on energy-awareness and its basic functional requirements are designed and proposed for real-time home energy monitoring service, reducing or cutting off standby power caused by home appliances, and intelligent home energy management service.

System Design Considerations for a ZigBee RF Receiver with regard to Coexistence with Wireless Devices in the 2.4GHz ISM-band

At the present time the task of designing a highly integrated ZigBee radio frequency (RF) receiver with an excellent coexistence performance is still very demanding and challenging. This paper presents a number of system issues and design considerations for a ZigBee RF receiver, namely IEEE 802.15.4, for coexistence with wireless devices in the 2.4-GHz ISM-band. With regard to IEEE 802.15.4, the paper analyzes receiver performance requirements for; system noise figure (NF), system third-order intercept point (system-IIP3), local oscillator phase noise and selectivity. Based on some assumptions, the paper illustrates the relationship between minimum detectable signal (MDS) and various situations that involve the effects of electromagnetic interference generated by other wireless devices. We infer the necessity of much more stringent specification requirements than the published standard for various wireless communication field environments

A Single Sideband RF-Modulator for Digital-IF Transmitter

The limitation of the single-sideband rejection ratio (SSRR) performance of transmitters based on I/Q mismatching due to high frequency signals has been investigated. The proposed single-sideband radio frequency-modulator (SSM) is capable of generating a single sideband frequency without implementing a quadrature local oscillator which displaces a phase of a local oscillating signal by 90deg at a high frequency. This technique is promising for radio transmission with a SSRR of more than 60 dBc. Also, the architecture of digital-intermediate frequency transmitter using the proposed SSM can be applied for a future software-defined radio solution supporting multiband and multimode wireless communications.

A Fully Integrated SoC with Digital MAC Processor and Transceiver for Ubiquitous Sensor Network at 868/915 MHz

SUMMARY A single-chip ubiquitous sensor network (USN) systemon-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed singlechip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver’s analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), intersymbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and −99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.

Network Bridge System for Interoperation of ZigBee-UPnP Network

Universal Plug and Play (UPnP) is one of the most promising home network middleware technologies because of its straightforward implementation and zero configuration characteristics. However, it has a limitation of the operations only IP based network and proceeding in a single IP subnet. In this paper, we proposed network bridge architecture for UPnP network to interoperate heterogeneous network, UPnP and ZigBee. The proposed network bridge architecture is capable of configuration ZigBee device as a virtual UPnP device. This technique is promising for seamless inter-networking with ZigBee and UPnP network. Also, the architecture of the proposed network bridge architecture can be applied for a future smart home.

Seamless Network Bridge for Supporting Interoperability UPnP-ZigBee

Universal Plug and Play (UPnP) can be applied many home appliances because of its straightforward implementation and zero configuration characteristics. However, it has limitation of the cost and spatial because it has to be used in IP based network. The proposed network bridge is capable of generating virtual Zigbee device without implementing each actual device which inserts an UPnP stack. This technique is promising for seamless inter-networking with Zigbee and UPnP network. Also, the architecture of the proposed network bridgecan be applied implementation for a future smart home.

Design and Implementation of AISG Modem for Antenna Line Device

In this paper, we propose a digital implementation of the antenna interface standards group (AISG) modem for the remote control and monitoring of antenna line devices (ALDs) through an antenna feeder cable. The proposed modem is implemented in Altera EP3C16E144C8 device, together with an 8-bit ADC and a BPF. It operates at variable data rates of 9.6, 38.4, and 115.2 kbps based on the OOK modulation scheme. The carrier frequency of the OOK modulated signals is 2.176 MHz. The modem is fully compliant with the 3GPP and AISG standards. To show the validity of the proposed AISG modem, the modem is implemented in FPGA and its functionality is verified using the verification scenario of 3GPP and AISG standards. The proposed AISG modem consumes 0.41 W and 0.6 W with DC power supplies of 10 V and 32 V, respectively. The measured transmit power level is +3.3 dBm, and the measured return loss in pass-band is more than 10 dB. The duty cycle variations for data rates of 9.6, 38.4, and 115.2 kbps are less than ±1 %, ±2 %, and ±4 %, respectively.

TOF Depth Camera Based 3D Gesture Interaction System

Active research is underway on virtual touch screens that complement the physical limitations of conventional touch screens. This paper discusses a virtual touch screen that uses a multi-layer perceptron to recognize and control three-dimensional (3D) depth information from a time of flight (TOF) camera. This system extracts an object’s area from the image input and compares it with the trajectory of the object, which is learned in advance, to recognize gestures. The system enables the maneuvering of content in virtual space by utilizing human actions.