Hag-Ju Cho

High-performance TaN/HfSiON/Si metal-oxide-semiconductor structures prepared by NH3 post-deposition anneal

Electrical and chemical characteristics of metal-oxide semiconductor field-effect transistors (MOSFETs) prepared by low-thermal-budget (∼600u200a°C) NH3 post-deposition annealing of HfSiON gate dielectric have been investigated. Compared to control Hf-silicate, HfSiON showed excellent thickness scalability, low leakage current density (J), and superior thermal stability. With proper annealing-time optimization, effective oxide thickness as low as 9.2 A with J<100u2009mA/cm2 at gate voltage Vg=−1.5u2009V has been achieved. C–V hysteresis of HfSiON MOSFET was found to be small (<20 mV). Unlike NH3 surface nitridation (NH3 pre-treatment prior to Hf-silicate deposition), no degradation in Gm (transconductance), Id–Vg (drain current–gate voltage), or Id–Vd (drain current–drain voltage) characteristics has been observed.

Improvement of surface carrier mobility of HfO/sub 2/ MOSFETs by high-temperature forming gas annealing

The surface electron mobility of HfO/sub 2/ NMOSFETs with a polysilicon gate electrode was studied in terms of the effects of high-temperature forming gas (FG) annealing. The high-temperature FG annealing significantly improved the drive current or the surface electron mobility of the NMOSFETs. Improvements were also observed in the subthreshold swings and the C-V characteristics, indicating a reduction in interfacial state density (D/sub it/). The D/sub it/ reduction was quantitatively confirmed by charge pumping current measurements. The mobility enhancement was achieved without degrading the equivalent oxide thickness (EOT) or gate leakage current. Different surface preparations, such as NH/sub 3/ or NO annealing, were explored to examine their effects on the NMOSFET performance. Mobility enhancement due to high-temperature FG annealing was also observed on these samples. Whereas NH/sub 3/ surface nitridation was effective in scaling EOT, the NO-annealed sample exhibited the highest mobility. Similar improvements were also observed on HfO/sub 2/ PMOSFETs, in terms of subthreshold swings, drive current, and surface hole mobility.

Structural and electrical properties of HfO 2 with top nitrogen incorporated layer

A novel technique to control the nitrogen profile in HfO/sub 2/ gate dielectric was developed using a reactive sputtering method. The incorporation of nitrogen in the upper layer of HfO/sub 2/ was achieved by sputter depositing a thin Hf/sub x/N/sub y/ layer on HfO/sub 2/, followed by reoxidation. This technique resulted in an improved output characteristics compared to the control sample. Leakage current density was significantly reduced by two orders of magnitude. The thermal stability in terms of structural and electrical properties was also enhanced, indicating that the nitrogen-doped process is effective in preventing oxygen diffusion through HfO/sub 2/. Boron penetration immunity was also improved by nitrogen-incorporation. It is concluded that the nitrogen-incorporation process is a promising technique to obtain high-k dielectric with thin equivalent oxide thickness and good interfacial quality.

Evaluation of silicon surface nitridation effects on ultra-thin ZrO2 gate dielectrics

The effects of silicon surface nitridation on metal–oxide–semiconductor capacitors with zirconium oxide (ZrO2) gate dielectrics were investigated. Surface nitridation was introduced via ammonia (NH3) annealing prior to ZrO2 sputter-deposition, and tantalum nitride (TaN) was used for the gate electrode. It was found that capacitors with the nitridation had thinner equivalent oxide thickness (∼8.7 A), comparable leakage current, and slightly increased capacitance–voltage hysteresis as compared to samples without nitridation. Additionally, transmission electron microscopy pictures revealed that nitrided samples had a thicker interfacial layer (IL), which had a higher dielectric constant than that of the non-nitrided IL.

High-k dielectrics and MOSFET characteristics

High dielectric constant materials have been investigated for gate dielectric applications. In this paper, various techniques (e.g. optimization of interfacial layer, N and Si incorporation and optimized profiles, forming gas anneal) for improving channel mobility, EOT scaling and reliability of high-k devices is discussed.

Achieving Conduction Band-Edge Effective Work Functions by

Conduction band-edge effective work functions (phi_m,eff) are demonstrated with TaC_x and TiN by means of La₂O₃ capping of HfSiO_x in a gate-first process flow with CMOS-compatible thermal budget. With TaC_x, a 10- Aring-thick La₂O₃ cap results in a phi _m,eff of 3.9 eV with a low equivalent oxide thickness (EOT) increase (1-2 Aring) and unaffected electron mobility. With TiN, non-nitrided La₂O₃ capping results in a smaller phi_m,eff reduction at a larger EOT increase, while with post-cap nitridation, the TiN phi_m,eff is lower at a smaller EOT increase. Results show that the choice of metal and nitridation conditions have significant effects on La₂O₃ capped stacks

\hbox{La}_{2}\hbox{O}_{3}

The novel technique to control the V/sub th/ of n/pMOS for HfSiO(N) in both poly-Si and MIPS (metal inserted poly-Si stack) gates is demonstrated. By adding AlO/sub x/ on HfSiO prior to poly-Si deposition, we successfully achieve symmetrical V/sub th/, values of 0.52V (nMOS), /-0.51V (pMOS) and high performance as I/sub on/, of 423uA/um for nMOS and 207uA/um for pMOS at I/sub off/=20pA/um. In addition, we find out that the ultra-thin and conformal TaN layer in MIPS gate does not contribute to the gate work function. By optimizing the TaN thickness, similar V/sub th/ values, compared to poly-Si gate, are achieved. Consequently, the measured saturation currents at I/sub off/=20pA/um are 430uA/um for nMOS and 250uA/um for pMOS. Both issues of PBTI for HfSiO/AlO/sub x//poly-Si structure and NBTI for HfSiO/AlO/sub x//MIPS structure are resolved by optimizing the post deposition annealing condition and using ozone interfacial oxide, respectively.

Capping of Hafnium Silicates

A novel technique to tailor the nitrogen profile in HfO/sub 2/ gate dielectric has been developed. Nitrogen was incorporated in the upper layer of HfO/sub 2/ using a reactive sputtering method, followed by a reoxidation anneal. The resulting dielectrics showed good thermal stability, boron penetration suppression, low interfacial trap density, plus lower hysteresis and improved MOSFET characteristics, in comparison to both non-nitrided and bottom nitrided (via Si-surface nitridation with NH/sub 3/) devices.

A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control

Optimization of fabrication process in obtaining high-quality HfSiON gate-oxide metal-oxide semiconductor field-effect transistors (MOSFETs) by NH/sub 3/ post-deposition anneal (PDA) has been performed. At 600/spl deg/C anneal temperature, a longer anneal duration resulted in reduced leakage current density (J), reduced trapped charges, and lower hysteresis in capacitance-voltage curves, but with a slight increase in effective oxide thickness (EOT). Subsequent interfacial layer growth with longer anneal duration was attributed to the increase in EOT. MOSFET, fabricated by the optimized process of 600/spl deg/C, 40 s NH/sub 3/ PDA, showed superior I/sub d/--V/sub d/ (drain current-drain voltage) and charge-trapping characteristics as compared to control Hf-Silicate.

Novel nitrogen profile engineering for improved TaN/HfO/sub 2//Si MOSFET performance

Hafnium oxynitride (HfO/sub x/N/sub y/) film was prepared and characterized for gate dielectrics application with EOT<10 /spl Aring/ for the first time. Thermal stability and crystallization during the subsequent thermal process were improved significantly by using HfO/sub x/N/sub y/ over HfO/sub 2/. Furthermore, excellent transistor characteristics were obtained for both p and nMOSFETs.