C. S. Kang

Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).

High-performance TaN/HfSiON/Si metal-oxide-semiconductor structures prepared by NH3 post-deposition anneal

Electrical and chemical characteristics of metal-oxide semiconductor field-effect transistors (MOSFETs) prepared by low-thermal-budget (∼600 °C) NH3 post-deposition annealing of HfSiON gate dielectric have been investigated. Compared to control Hf-silicate, HfSiON showed excellent thickness scalability, low leakage current density (J), and superior thermal stability. With proper annealing-time optimization, effective oxide thickness as low as 9.2 A with J<100 mA/cm2 at gate voltage Vg=−1.5 V has been achieved. C–V hysteresis of HfSiON MOSFET was found to be small (<20 mV). Unlike NH3 surface nitridation (NH3 pre-treatment prior to Hf-silicate deposition), no degradation in Gm (transconductance), Id–Vg (drain current–gate voltage), or Id–Vd (drain current–drain voltage) characteristics has been observed.

High-k dielectrics and MOSFET characteristics

High dielectric constant materials have been investigated for gate dielectric applications. In this paper, various techniques (e.g. optimization of interfacial layer, N and Si incorporation and optimized profiles, forming gas anneal) for improving channel mobility, EOT scaling and reliability of high-k devices is discussed.

Interfacial defect states in HfO/sub 2/ and ZrO/sub 2/ nMOS capacitors

A comprehensive analysis of the bump/kink observed in the experimental capacitance-voltage (C-V) curves of HfO/sub 2/ and ZrO/sub 2/ capacitors was performed using self-consistent numerical simulations. Both HfO/sub 2/ samples grown by sputter deposition and grown by metal-organic chemical vapor deposition (MOCVD) were examined. The bumps in the C-V curves were found to be consistent with an interface state centered 0.25 eV above the valence bandedge for the sputter deposited devices, and 0.30 eV above the bandedge for the MOCVD devices. Annealing of the HfO/sub 2/ devices reduced the densities of these traps, but also increased the effective oxide thickness. Similar defect states were detected for the ZrO/sub 2/ devices centered 0.25 eV above the valence bandedge.

Optimized NH/sub 3/ annealing Process for high-quality HfSiON gate oxide

Optimization of fabrication process in obtaining high-quality HfSiON gate-oxide metal-oxide semiconductor field-effect transistors (MOSFETs) by NH/sub 3/ post-deposition anneal (PDA) has been performed. At 600/spl deg/C anneal temperature, a longer anneal duration resulted in reduced leakage current density (J), reduced trapped charges, and lower hysteresis in capacitance-voltage curves, but with a slight increase in effective oxide thickness (EOT). Subsequent interfacial layer growth with longer anneal duration was attributed to the increase in EOT. MOSFET, fabricated by the optimized process of 600/spl deg/C, 40 s NH/sub 3/ PDA, showed superior I/sub d/--V/sub d/ (drain current-drain voltage) and charge-trapping characteristics as compared to control Hf-Silicate.

The effects of nitrogen and silicon profile on high-k MOSFET performance and Bias Temperature Instability

Nitrogen profile has been modulated by inserting Si layer into HfO/sub x/N/sub y/. In this paper, the effects of nitrogen and silicon on MOSFET performance and BTI (Bias Temperature Instability) characteristics have been investigated. Nitrogen incorporation enhanced V/sub TH/ shift for both PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability). However, BTI degradation is significantly suppressed by the Si insertion. This improvement can be attributed to the reduction of oxide bulk trapped as well as interface trapped charge generation resulting from the insertion of Si layer.

Impact of NH/sub 3/ pre-treatment on the electrical and reliability characteristics of ultra thin hafnium silicate films prepared by re-oxidation method

The trade-offs between the benefits of NH/sub 3/ pre-treatment such as improved scalability, lower leakage and higher breakdown fields, and potential issues such as large hysteresis, degraded MOSFET characteristics and poorer reliability on Hf-silicate devices have been studied.

Hafnium-based high-k dielectrics

Hafnium-based high-K dielectrics such as HfO/sub 2/, HfON and HfSiON have attracted a great deal of attention because of their potential for successful integration into CMOS technology. However, channel mobility degradation, charge trapping and reliability are major concerns. In this paper, we review our recent research results, namely, the charge trapping characteristics, the effects of nitrogen on minority carrier lifetime and channel mobility, and Hf-Ti-O dielectrics. We have investigated how N affects the minority carrier lifetime in the Si substrate and how it relates to /spl mu//sub eff/. A new dielectric stack consists of TiO/sub 2//HfO/sub 2/ bi-layer has shown improved thermal stability and increased K value (thus scaled EOT < 1.0nm) without the disadvantages of incorporated N.

Application of top HfSiON layer for improved poly-gated HfO/sub 2/ PMOSFET performance

In this paper, application of amorphous HfSiON layer on HfO/sub 2/ was evaluated for improved poly-Si gated HfO/sub 2/ PMOSFET performance.HfSiON process by reoxidation method was developed and the effects of its use as a top layer of HfO/sub 2/ for PMOSFET were investigated. The top HfSiON layer was demonstrated to improve the characteristics of PMOSFET through better thermal stability and immunity to boron diffusion compared to HfON.

Polarity dependence of the reliability characteristics of HfO/sub 2/ with poly-Si gate electrode

In this paper, polysilicon gate electrode was used in order to investigate the effects of both electron and hole injection from the gate. HfO/sub 2/ was directly deposited on Si-substrate without any intentional interface layer. In addition to polarity dependence of HfO/sub 2/breakdown characteristics, charge trapping behavior under unipolar AC stressing, and bias temperature instability under gate injection and substrate injection have been investigated.