J. C. Lee

Electrical and spectroscopic comparison of HfO2/Si interfaces on nitrided and un-nitrided Si(100)

The interfacial chemistry of the high-k dielectric HfO2 has been investigated on nitrided and un-nitrided Si(100) using x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). The samples are prepared by sputter depositing Hf metal and subsequently oxidizing it. A 600 °C densification anneal is critical to completing Hf oxidation. These spectroscopic data complement electrical testing of metal oxide semiconductor capacitors fabricated with ∼50 A HfO2 on nitrided and un-nitrided Si(100). Capacitors with interfacial nitride show reduced leakage current by a factor of 100 at a −1 V bias. Concurrently, interfacial nitride increased capacitance 12% at saturation. XPS shows that an interfacial layer composed of nonstoichiometric hafnium silicate (HfSixOy), forms at both the HfO2/Si and HfO2/SiNx interfaces. Differences in the Si 2p and O 1s XP spectra suggest more silicate forms at the un-nitrided interface. HfO2 films on un-nitrided Si show more O 1s and Si 2p photoemission intensity...

Metal-oxide-semiconductor capacitors on GaAs with high-k gate oxide and amorphous silicon interface passivation layer

We demonstrate the electrical properties of metal-oxide-semiconductor capacitors on molecular beam epitaxial GaAs in situ passivated with ultrathin amorphous Si (a-Si) layer and with ex situ deposited HfO2 gate oxide and TaN metal gate. Minimum thickness of the Si interface passivation layer of 1.5 nm is needed to prevent the Fermi level pinning and provide good capacitance-voltage characteristics with equivalent oxide thickness of 2.1 nm and leakage current of ⩽1.0mA∕cm2. Transmission electron microscopy analysis showed that the Si layer was oxidized up to 1.4 nm during ex situ processing while the interface between the GaAs and a-Si remained atomically sharp without any sign of interfacial reaction.

Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application

Physical, electrical and reliability characteristics of ultra thin HfO/sub 2/ as an alternative gate dielectric were studied for the first time. Crucial process parameters of oxygen modulated dc magnetron sputtering were optimized to achieve an equivalent oxide thickness (EOT) of 11.5 /spl Aring/ without deducting the quantum mechanical effect. Leakage current was 3/spl times/10/sup -2/ A/cm/sup 2/ at +1 V. Excellent dielectric properties such as high dielectric constant, low leakage current, good thermal stability, negligible dispersion and good reliability were demonstrated.

MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si

MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si have been investigated. Thin equivalent oxide thickness (EOT), low leakage, negligible frequency dispersion, interface density less than 10/sup 11/ cm/sup -2/ eV/sup -1/, small hysteresis, excellent reliability characteristics have been demonstrated. The ZrO/sub 2/ film has been shown to be amorphous. A thin interfacial Zr-silicate layer (k>8) exists and is beneficial in maintaining good interfacial quality. This Zr-silicate layer grows after annealing and can be minimized through process optimization. Well-behaved p-channel MOS transistor characteristics with a subthreshold swing of 80 mV/decade have also been achieved.

A model for electrical conduction in metal‐ferroelectric‐metal thin‐film capacitors

Time‐zero current‐voltage characteristics and time‐dependent current behavior of metal‐ferroelectric‐metal (Pt‐PZT‐Pt) capacitor structures have been studied. Under constant‐voltage stressing, the current density through the 1500‐A‐thick lead‐zirconate‐titanate (PZT) film exhibits a power‐law dependence on time, with the exponent (∼0.33) independent of temperature and voltage. Electrode material dependence of current density indicates that the conventional model of trap‐limited single‐carrier injection over nonblocking contacts is inadequate to explain the time‐zero current. A change in top electrode material from Pt to In leads to the observation of work‐function‐driven Schottky contacts between the metal and ferroelectric. The current‐voltage characteristics fit a two‐carrier injection metal‐semiconductor‐metal model incorporating blocking contacts, with distinct low‐ and high‐current regimes (PZT is assumed to be p‐type and trap‐free in this model). Temperature‐dependent I‐V measurements indicate a Pt‐...

Electrical properties of ZrO2 gate dielectric on SiGe

We report the electrical properties of a high dielectric constant (high-k) material, ZrO2, deposited directly on SiGe, without the use of a Si buffer layer or a passivation barrier. ZrO2 thin films of equivalent oxide thickness (EOT) down to 16.5 A were deposited on strained SiGe layers by reactive sputtering. Results indicate that ZrO2 films on SiGe have good interfacial properties and low leakage currents. Sintering in forming gas at 350 °C for 1 h could further improve the film quality. Although threshold voltage stability and dielectric dispersion become a concern for thick ZrO2 films, thin ZrO2 films of EOT less than 20 A exhibit excellent electrical properties making them a good candidate for SiGe applications.

Characterization of resistivity and work function of sputtered-TaN film for gate electrode applications

Tantalum nitride (TaN) films were prepared by reactive sputtering in a gas Ar and N2 for gate electrode applications. Resistivity, crystallinity, and work function of the films were investigated as a function of nitrogen flow rate. As the nitrogen flow rate increased from 0 to 20 sccm, the resistivity of as-deposited TaN films increased from 132 to 1.4×105 μΩ cm. With a nitrogen flow rate of 8 and 10 sccm, the fcc TaN phase was obtained. The work function of the TaN films was investigated using TaN-gated nmetal–oxide–semiconductor capacitors with SiO2 gate dielectrics of various thicknesses. As the nitrogen flow rate increased from 4 to 12 sccm, the work function decreased from 4.1 to 3.4 eV for as-deposited films. After annealing at 950 °C for 1 min, the work function increased to 4.5–4.7 eV, with less dependency on the nitrogen flow rate.

Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 /spl Aring/-12 /spl Aring/)

MOSFETs with equivalent oxide thickness of 8-12 /spl Aring/ have been demonstrated by using high-K gate dielectric thin films (HfO/sub 2/) and TaN gate electrode. Both self-aligned (higher thermal budget process) and non-self-aligned process (low thermal budget as in the replacement gate process) were used and compared. Excellent electrical characteristics (e.g. S/spl sim/68 mV/dec) and reliability characteristics (e.g. high E/sub BD/, low charge trapping and SILC) were also obtained.

Electrical and physical characteristics of ultrathin hafnium silicate films with polycrystalline silicon and TaN gates

Metal-oxide-semiconductor transistors of ultrathin hafnium silicate films (equivalent oxide thickness (EOT) of 12.5–14 A) with polycrystalline silicon and metal (TaN) gates have been demonstrated. Well-behaved transistor characteristics and EOT stability of Hf silicate with n+ polysilicon indicates good compatibility with polysilicon gate process without use of barrier layer. Transmission electron microscopy analysis indicates that the films have no top interfacial layer with both TaN and polysilicon gates. The films also remain amorphous and show no indication of phase separation even after a 950 °C dopant activation anneal. Hf silicate films also show excellent transistor characteristics with TaN gate. NH3 pretreatment results in degraded transistor characteristics for TaN and poly gate samples. Good capacitance–voltage characteristics and negligible hysteresis (<10 mV) was observed in the capacitors after a 1000 °C activation indicating good electrical stability at high temperatures and minimal charge ...

High-quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs with TaN electrode and nitridation surface preparation

A surface preparation technique using an NH/sub 3/ anneal has been investigated to reduce interface reaction and consequently the equivalent oxide thickness (EOT) of hafnium oxide for alternative gate dielectric applications. MOSCAPs and MOSFETs were fabricated on the NH/sub 3/ nitrided substrates with HfO/sub 2/ dielectric and TaN gate electrode. Using this nitridation technique, EOT of as thin as 7.1 /spl Aring/ with 10/sup -2/ A/cm/sup 2/ at -1.5 V was obtained. Furthermore, excellent device characteristics and reasonable reliability have been achieved.