Hai Au Huynh

Modeling of FinFET Parasitic Source/Drain Resistance With Polygonal Epitaxy

In this paper, we introduce a new compact model of the parasitic resistance of a FinFET with a hexagonal-shaped raised source–drain (S/D) structure. In contrast to previous models that divided the extrinsic S/D region into three parts, we redefined the region boundaries and modeled them as a series connection of accumulation resistance, gradient resistance, bulk resistance, and contact resistance. The newly added bulk resistance model accounts for the highly doped silicon region. We also significantly improved the contact resistance model to reflect the contact area and contact resistivity for better accuracy in the raised S/D region. We validated the accuracy of our model by varying the gate voltage, doping diffusion length, epitaxy silicon height, and contact resistivity, finding the model errors to be within 2% of the 3-D technology CAD device simulation results.

Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods

Direct power injection (DPI) and bulk current injection (BCI) methods are defined in IEC 62132-3 and IEC 62132-4 as the electromagnetic immunity test method of integrated circuits (IC). The forward power measured at the RF noise generator when the IC malfunctions is used as the measure of immunity level of the IC. However, the actual power that causes failure in ICs is different from forward power measured at the noise source. Power transfer efficiency is used as a measure of power loss of the noise injection path. In this paper, the power transfer efficiencies of DPI and BCI methods are derived and validated experimentally with immunity test setup of a clock divider IC. Power transfer efficiency varies significantly over the frequency range as a function of the test method used and the IC input impedance. For the frequency range of 15 kHz to 1 GHz, power transfer efficiency of the BCI test was constantly higher than that of the DPI test. In the DPI test, power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. When performing the IC immunity tests following the standards, these characteristics of the test methods need to be considered.

EM noise immunity enhancement using Schmitt Trigger logic gates in CMOS process

The electromagnetic interference (EMI) problem can be resolved in different levels in system design, such as package, circuit and gate level. In this work, we propose and validate a digital logic gate design method to improve EMI performance of digital circuits. We propose one-sided hysteresis dynamic threshold MOSFET (DTMOS) Schmitt Trigger (S. T.) logic gates that can be implemented in standard 0.18 μm CMOS logic process. In order to overcome the limitation of small hysteresis width, two additional transistors are added in a unit gates structures. The building blocks of digital circuits such as buffer, NAND and NOR gates are fabricated and the hysteresis transfer characteristics are measured and confirmed.

An experimental study of EMI reduction of DC-DC converter with frequency hopping technique

In this paper, the EMI problem of the DC-DC converter is discussed. The power spectrums of the DC-DC converters nodes are analyzed and the noise scanner method is used to prove that the switching node of the DC-DC converter is the dominant source of EMI. To reduce EMI of DC-DC converters, frequency hopping technique can be applied. The DC-DC converter with frequency hopping technique is fabricated using 180nm CMOS process. The test chip results by IC-stripline and noise scanner methods show a significant improvement in EMI. The EMI reduction amount is 6.87 dB at fundamental switching frequency by applying the frequency hopping technique with IC-stripline measurement.

A new pinwheel meander-perforated plane structure for noise suppression in system-on-package

As the market of wearable and internet of things (IoT) expands, there is a strong demand of shrinking the size of System-on-Package (SoP). In this paper, we propose a new electromagnetic bandgap structure (EBG) to mitigate the noise coupling within SoPs. EBGs have been widely used in printed circuit boards (PCB). Thus, the EBG size reduction is critical for integrating it in the package. The proposed structure has a unique noise suppressing pinwheel meander perforated plane structure (PMPP) that can be used in small size package. Critical problem of EBGs size reduction is shifting the suppression frequency to higher. Therefore, we propose to combine the EBG structure, meander-line, and pinwheel shaped patch to reduce size of EBG unit cell from 12.2mm×12.2mm to 2.44mm×2.44mm while maintaining the suppression frequency and bandwidth. The stop band bandwidth of proposed structure is 3.58∼12.83GHz.

Design and optimization of inductive snubber for DC-DC converter

Switching operations of the DC-DC converter is the major source of electromagnetic emission (EMI) of power management circuits. In this paper, a design guideline for inductive snubber circuit is developed to reduce EMI of DC-DC converter. A switching loop of the DC-DC converter is modeled and ringing noise on the switching node is analyzed. Circuit schematic simulation is performed to verify the effectiveness of the EMI suppression and to optimize the suppression effect.

Modified pinwheel meander-line perforated plane structure for system-in-package

Conventionally, EBG structures are used in the printed circuit boards (PCBs) level [1]. We proposed the Pinwheel Meander-line Perforated Plane (PMPP) structure as the solution [2]. In this paper, we modify the PMPP to reduce the area and electromagnetic emission (EMI). By reducing the thickness of dielectric layers and plane from 30μm to 10μm, we reduce the number of meander-line curves from 5 to 1, and the number of unit cells from 3 to 2. We confirm the electromagnetic compatibility (EMC) property through simulation, using 3D electromagnetic (EM) solver. The stopband frequency range of this proposed structure is 3.53∼22.69GHz, which is wider than 3.58∼12.83GHz, the stopband of the previous PMPP.

EMC Qualification Methodology for Semicustom Digital Integrated Circuit Design

In this paper, a simulation methodology and an electromagnetic compatibility qualification environment (EQE) are developed to verify the electromagnetic susceptibility of semicustom digital integrated circuits (IC) during the design phase. The immunity levels of the digital circuits are estimated by the functional failure and delay change caused by the external noise which is injected by bulk current injection (BCI) and direct power injection (DPI) methods. The model for the device under test (DUT), the standard cell parasitic model, and the equivalent circuit model of BCI and DPI test setup are developed for the IC immunity test. All test components and on-chip circuit models are linked by EQE to analyze the target DUT. The EQE can be applied to predict the immunity level of the design at the schematic level and postlayout level design. To validate the accuracy of the proposed simulation tool, EQE is applied to the design process of a clock divider (CKD) and a serial peripheral interface (SPI) circuits to verify their immunity levels. The CKD and SPI circuits are designed and fabricated using Magna 180 nm Complementary metal-oxide semiconductor (CMOS) technology. The immunity levels generated by the EQE are compared with the experimental measurement results. The comparison shows good agreement between simulation and measurement.

Design of on-chip power noise sensing circuit and its applications

The fluctuations on power supply lines affect the operation and performance of the integrated circuits such as timing mismatches and functional failures. In this paper, we propose, implement and measure a sensing circuit to measure the peak of the overshoot and undershoot of the power supply noise. Using the sensing circuit output results, the magnitude of the actual noise coupled inside the on-chip power distribution network can be identified, and the probability of failure can be predicted. In the embedded sensing circuit, the analog noise is processed on-chip and is encoded to a digital value. Therefore, the limitations of PAD and the bonding wire parasitics are eliminated and better measurement accuracy can be achieved. The proposed sensing circuit was fabricated using 180nm CMOS process, the test flow for using sensing circuit was proposed, and was applied to measure the the peak overshoot and undershoot of power supply noise of an I/O transmitter circuit in operation. The measurement results of overshoot and undershoot of transmitters switching noise are 2.6V and 1.1V, respectively for 1.8V supply voltage. The sensing circuit is also applied to measure the magnitude of the on-chip noise caused by externally injected EMI noise using bulk current injection (BCI) method.