Eun-Seok Song

Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform

As mobile hand-held devices including mobile phone are required to provide multi-media services more and more, it is necessary that the various hardware including high speed memory, high capacity data storage device, and high performance logic processor are integrated into the limited volume, which results in high density 3D SIP. In this work, power delivery network for 3D SIP integrated on silicon interposer will be discussed. The silicon interposer used in 3D SIP includes integrated decoupling capacitor, which gives good power delivery performance.

Model-order estimation and reduction of distributed interconnects via improved vector fitting

This paper introduces an automated method estimating and reducing the order of macromodel for fast transient simulation. The proposed method improves the vector fitting algorithm for extracting the reduced-order macromodel from the accurate macromodel having redundant poles and residues. The performance of the proposed method has been demonstrated through several test cases.

Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design

In this paper, we introduce a new, highly accurate, package parasitics estimation technique (PME: package model estimator) that can simultaneously consider both on-chip and off-chip parasitic effects at the early stage of chip design. The performance of the proposed technique was verified by application to a substrate package designed for mass production. This paper mainly focuses on the estimation of electrical models of unrouted PCB traces in the early stage of package design by the use of the weighting factor (W) reflecting the irregular routability of a substrate design. It is clearly shown that the proposed estimation algorithm produces excellent results compared to the post-simulation models for simple as well as complicated package designs. The efficient chip-package co-design technique, which accounts for all necessary parasitic effects of the package, can accurately predict the upper and lower boundaries of the noise margin for worst cases

A new EBG structure for < 5 GHz SSN suppression in < 10mm x 10mm high density mixed-signal SIP

In modern mobile hand-held phone, many kinds of wireless services are employed. For example, there are blue tooth, mobile TV, wireless broadband internet, HSDPA, RF-ID, and etc. Since the small-form factor chip set solution corresponding to each wireless service is strongly required in ultra-thin small form-factor mobile phone, system in package (SIP) is promising solution. In mixed signal SIP (MS-SIP) integrating digital logic IC and RF-IC, noise isolation between digital and RF domain is becoming one of major concerns. To manage RF noise propagation, one of recently presented noise suppression design technology is power delivery network (PDN) with electromagnetic band-gap (EBG). In this paper, a new EBG structure employable to small form factor (<10mm times 10mm) MS-SIP is presented.