Hai Bing Yin

A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders

High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. This paper proposes an efficient very large scale integration architecture for integer multi-resolution motion estimation based on optimized algorithm. There are three major contributions in this paper. First, this paper proposes a hardware friendly multi-resolution motion estimation algorithm well-suited for high definition video encoder. Second, parallel processing element (PE) array structure is proposed to implement three-level hierarchical motion estimation, only 256PEs are enough for one reference frame real-time high definition motion estimation by efficient PE reuse. Third, efficient on-chip reference pixel buffer sharing mechanism between integer and fractional motion estimation is proposed with almost 50% SRAM saving and memory bandwidth reduction. The proposed multi-resolution motion estimation algorithm reached a good balance between complexity and performance with rate distortion optimized variable block size motion estimation support. Also, we have achieved moderate logic circuit and on-chip SRAM consumption. The proposed architecture is well-suited for all MPEG-like video coding standards such as H.264, audio video coding standard, and VC-1.

Efficient macroblock pipeline structure in high definition AVS video encoder VLSI architecture

In traditional four-stage pipeline structures for H.264 video encoder hardware implementation, rate distortion optimization (RDO) based mode decision was turned off, and dual-port or ping-pang on-chip search window SRAM was used to achieve data reuse between the integer and fractional pixel motion estimation. To support RDO based mode decision for efficient high definition AVS video coding implementation, we propose an improved four-stage MB pipeline structure. Also on-chip buffer structure is optimized to achieve the balance between circuit consumption and coding performance. The Jizhun profile AVS video encoder is successfully mapped into hardware implementation with the proposed pipeline structure with small performance degradation.

VLSI friendly me search window buffer structure optimization and algorithm verification for high definition H.264/AVS video encoder

High external memory bandwidth requirement is one major challenge for efficient hardware motion estimation (ME) implementation. Large double-buffered on-chip search window (SW) buffer is usually employed to increase the throughput. In this paper, we focus on SW buffer structure optimization in a systematic viewpoint. An efficient buffer share mechanism is proposed to minimize the memory consumption, simultaneously alleviate the external memory access bandwidth. Moreover, variable block size ME (VBSME) and large SW in high definition (HD) video encoder are both supported with good trade off among throughput, data regularity, and rate distortion performance. The simplified algorithm can achieve nearly 50% SW buffer saving with less than 0.15dB PSNR degradation at the worst case compared with full search VBSME.

A highly efficient pipeline architecture of RDO-based mode decision design for AVS HD video encoder

Like H.264, AVS video coding standard also uses macroblock (MB) based motion compensation (MC) and mode decision (MD). Rate distortion optimization (RDO) is the best known mode decision method, but with a high computational complexity that limits its applications. In our paper, firstly an MD algorithm based on RDO is given, which makes more mode candidates enter into RDO mode decision with little hardware resource increment. We further analyze the pipeline structure in detail, and implement a block-level 5-stage hardware pipeline. It can support the real time RDO mode decision processing of 1080P@30fps, and the coding efficiency is about 0.5db higher than the traditional SAD method. Our design is described in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18-µm CMOS technology with 215K logic gates and 80 KB SRAMs.

A hardware-efficient architecture for multi-resolution motion estimation using fully reconfigurable processing element array

Integer motion estimation (IME) for block-based video coding presents a significant challenge in external memory bandwidth, data latency, and circuit area with the increase of coding complexity and video resolution. To conquer these problems, this paper proposes a hardware-efficient VLSI architecture for multi-resolution motion estimation algorithm (MMEA) based on fully reconfigurable processing element (PE) array. On-chip storage and PE array are carefully designed to support parallel computation and hardware resource sharing. In addition, low data latency is obtained by arranging internal logics in parallel according to the data dependency. As a result, our design can support real time processing of 1080P@30fps with 2 reference frames and a search range of 256×192 and it is implemented under SMIC 0.18-µm CMOS technology with 920K logic gates and 192 KB SRAMs. Compared with previous work, our design can achieve the best performance-price rate benefiting from the proposed re-configurable PE array.

Fast mode decision based on RDO for AVS high definition video encoder

In this paper, we propose a fast and effective mode decision (MD) algorithm based on rate distortion optimization (RDO) for AVS high definition video encoder. The fast algorithm is composed of two parts. Firstly, mode preselection based on sum of absolute difference (SAD) is employed to reduce modes for candidate so as to alleviate the dramatic throughout burden. Secondly, we adopt 4-way parallel scanning technique to reduce the cycles of each mode decision based on RDO. Theoretical analysis and experimental results show that the proposed fast algorithm can meet the needs of 720P and 1080P real-time high definition AVS video encoding. Besides, the mode pre-selection algorithm provides a similar performance to the all modes enabled algorithm. And the 4-way parallel technique using negligible extra resources increases the speed of coding bits estimation by 3.4 times than traditional techniques.

Algorithm analysis and architecture design for rate distortion optimized mode decision in high definition AVS video encoder

There are abundant intra and inter prediction modes in the AVS video coding standard. Rate distortion optimized mode decision can fully utilize this flexibility to improve the spatio-temporal prediction efficiency and maximize the coding efficiency. However, the implementation complexity is dramatically high due to huge throughput burden. Hardware oriented mode decision algorithm is tailored for VLSI implementation in this work for high definition video coding. Mode preselection is employed to alleviate the dramatic throughout burden. Also, intelligent pipeline scheduling mechanism is proposed to break the intrinsic data dependency in intra prediction, which is directly related with mode decision. The proposed simplified algorithm is well-suited for hardware implementation with small performance penalty. Finally, the VLSI architecture is proposed with good trade off between circuit consumption and rate distortion performance.

A Regular VLSI Architecture of Motion Vector Prediction for Multiple-Standard MPEG-Like Video Codec

Motion vector (MV) prediction and residue coding technique is adopted to fully utilize the motion field redundancy in the prevailing video standards, and MV prediction is desired in both video encoder and decoder. The computation burden for MV prediction is not very high. However, there is high irregularity in raw MV prediction algorithm with two-stage and four-level hierarchical tree control flows. It makes efficient VLSI architecture implementation challenging. The high irregularity is mainly derived from the abundant inter prediction modes including variable block size partition and temporal prediction direction, as well as the irregular control flow of the MV prediction algorithm. This paper proposes a highly regular architecture to implement MV prediction for multi-standard video codec. Complex control logic is simplified by regularly table look-up of the control parameters predefined and stored in on-chip tables. The parameters of the current macroblock (MB) and its neighboring blocks are initialized and refreshed in a regular manner. Moreover, pipelining and parallelism are employed in the proposed architecture to improve throughput efficiency and tradeoff between hardware cost and efficiency. Simulation results verify the effectiveness of the proposed design.

Adaptive integer-precision Lagrange multiplier selection for high performance AVS video coding

In AVS and H.264/AVC, Lagrangian Rate distortion (RD) optimization techniques are widely adopted for coding mode selection and displacement vector estimation. The optimal Lagrange multipliers in these two cases are both floating-point values. If RD optimized video encoder is implemented on computation-constrained fixed-point platform such as FPGA and ASIC, fixed-point Lagrange multiplier selection is an important problem to trade-off the RD performance and computation complexity. This work focuses on fixed-point Lagrange multiplier selection for RD mode decision. Adaptive scaling matrix is used to trade-off complexity and RD performance. Also, intensive simulation results and analysis on precision, hardware cost, and RD performance are given. The proposed approach is also well-suited for RD optimized motion estimation for computation-constrained video coding.

High throughput VLSI architecture for multiresolution integer motion estimation in high definition AVS video encoder

This paper proposes a hardware friendly multi-resolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and utilizing the high correlation in multi-resolution reference pixels, huge throughput and computation due to large search window are alleviated considerably. Sixteen way parallel processing element arrays with configurable multiplying technologies achieve fast search with regular data access and efficient data reuse. Also, the parallel arrays can be efficiently reused at three hierarchical levels for sequential motion vector refinement. The modified algorithm reaches a good balance between implementation complexity and search performance. Also, the logic circuit and on-chip SRAM consumption of the VLSI architecture are moderate.