Huizhu Jia

A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders

High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. This paper proposes an efficient very large scale integration architecture for integer multi-resolution motion estimation based on optimized algorithm. There are three major contributions in this paper. First, this paper proposes a hardware friendly multi-resolution motion estimation algorithm well-suited for high definition video encoder. Second, parallel processing element (PE) array structure is proposed to implement three-level hierarchical motion estimation, only 256PEs are enough for one reference frame real-time high definition motion estimation by efficient PE reuse. Third, efficient on-chip reference pixel buffer sharing mechanism between integer and fractional motion estimation is proposed with almost 50% SRAM saving and memory bandwidth reduction. The proposed multi-resolution motion estimation algorithm reached a good balance between complexity and performance with rate distortion optimized variable block size motion estimation support. Also, we have achieved moderate logic circuit and on-chip SRAM consumption. The proposed architecture is well-suited for all MPEG-like video coding standards such as H.264, audio video coding standard, and VC-1.

A comparison of fractional-pel interpolation filters in HEVC and H.264/AVC

The fractional-pel interpolation filter adopted in H.264/AVC improves motion compensation greatly. Recently, a new DCT-based fractional-pel interpolation filter is adopted in the oncoming standard HEVC. We are interested in the differences between these two types of fractional-pel interpolation filters. In this paper we describe the derivations of fractional-pel interpolation filters in HEVC and H.264/AVC in detail, and compare them on properties of frequency responses. We find that the half-pel interpolation filters in HEVC and H.264/AVC are very similar, but the low-pass properties of quarter-pel interpolation filters in HEVC are much better than those in H.264/AVC. Experimental results validate this phenomenon, the fractional-pel interpolation in H.264/AVC tends to increase BD-rates by more than 10% compared with that in HEVC, and this performance loss mainly comes from quarter-pel interpolation filters. On the other hand, the complexity of fractional-pel interpolation filtering in HEVC is greatly increased than that in H.264/AVC.

Efficient macroblock pipeline structure in high definition AVS video encoder VLSI architecture

In traditional four-stage pipeline structures for H.264 video encoder hardware implementation, rate distortion optimization (RDO) based mode decision was turned off, and dual-port or ping-pang on-chip search window SRAM was used to achieve data reuse between the integer and fractional pixel motion estimation. To support RDO based mode decision for efficient high definition AVS video coding implementation, we propose an improved four-stage MB pipeline structure. Also on-chip buffer structure is optimized to achieve the balance between circuit consumption and coding performance. The Jizhun profile AVS video encoder is successfully mapped into hardware implementation with the proposed pipeline structure with small performance degradation.

Hybrid Zero Block Detection for High Efficiency Video Coding

In this paper we propose an efficient hybrid zero block early detection method for high efficiency video coding (HEVC). Our method detects both genuine zero blocks (GZBs) and pseudo zero blocks (PZBs). For GZB detection, we use a two sum of absolute difference bounds and a one sum of absolute transformed difference threshold to decrease the GZB detection complexity. A fast rate-distortion estimation algorithm for HEVC is proposed to improve the PZB detection rate. Experimental results on the HM platform show that the proposed method saves about 50% of the rate-distortion optimization (RTO) time, with negligible Bjøntegaard delta bit rate loss. Our method is faster than other state-of-the-art ZB detection methods for HEVC by 10%-30%.

Multi-level low-complexity coefficient discarding scheme for video encoder

Rate-Distortion (R-D) optimization technique plays an important role in video coding. R-D sense discarding (thresholding) technique can make great improvement on the coding efficiency. This work first proposes a multi-level coefficient discarding scheme, which is composed of coefficient-level (CL), block-level and macroblock-level discarding. In CL, coefficient-level R-D cost function is formulated and then CL discarding scheme is developed. At last, an effective implementation method is proposed to reduce the complexity of the proposed scheme. The experimental results show that our proposed multi-level discarding scheme can improve the coding performance of video encoder by 0.15db in average.

Fast algorithm of coding unit depth decision for HEVC intra coding

The emerging high efficiency video coding standard (HEVC) achieves significantly better coding efficiency than all existing video coding standards. The quad tree structured coding unit (CU) is adopted in HEVC to improve the compression efficiency, but this causes a very high computational complexity because it exhausts all the combinations of the prediction unit (PU) and transform unit (TU) in every CU attempt. In order to alleviate the computational burden in HEVC intra coding, a fast CU depth decision algorithm is proposed in this paper. The CU texture complexity and the correlation between the current CU and neighbouring CUs are adaptively taken into consideration for the decision of the CU split and the CU depth search range. Experimental results show that the proposed scheme provides 39.3% encoder time savings on average compared to the default encoding scheme in HM-RExt-13.0 with only 0.6% BDBR penalty in coding performance.

Adaptive multi-resolution motion estimation using texture-based search strategies

Motion estimation is the most complex module which contributes nearly 70% of computation resources in a hardware-based video encoder. This huge computational complexity limits the performance of HD video encoders in terms of encoding speed and power consumption. This paper presents a hardware oriented multi-resolution motion estimation algorithm using adaptive search strategies to reduce computational complexity. The spatial homogeneity and the temporal stationarity characteristics of video sequences are adaptively detected to determine search range and down-sampling rate. Homogeneous regions are detected by using Sobel edge operators and stationary regions are detected by using temporal information. These texture-based search strategies make motion estimation more concise under fixed computational complexity constraint. Additional computational cost originated by determining the search strategies can be neglected due to the simple addition and shift operations. Experimental results show that the proposed algorithm achieves better performance and reduces computation cost by 40% compared with previous works.

An all-zero blocks early detection method for high-efficiency video coding

The High Efficiency Video Coding has a significant compression performance benefit versus previous standards. Thanks to the high efficiency prediction tools, blocks with all-zero quantized transform coefficients are quite common in HEVC. The computation load of transform and quantization can be remarkably reduced if the all-zero blocks can be detected prior to transform and quantization. Based on the theoretical analysis of the integer transform and quantization process in HEVC, we propose some SAD thresholds under which all-zero block can be detected. Simulation results show that with our proposed method, nearly 37% time saving for computation time of transform and quantization can be saved.

On a Highly Efficient RDO-Based Mode Decision Pipeline Design for AVS

Rate distortion optimization (RDO) is the best known mode decision method, while the high implementation complexity limits its applications and almost no real-time hardware encoder is truly full-featured RDO based. In this paper, first, a full-featured RDO-based mode decision (MD) algorithm is presented, which makes more modes enter RDO process. Second, the throughput of RDO-based MD pipeline is thoroughly analyzed and modeled. Third, a highly efficient adaptive block-level pipelining architecture of RDO-based MD for AVS video encoder is proposed which can achieve the highest throughput to alleviate the RDO burden. Our design is described in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18- μm CMOS technology with 232 K logic gates and 85 Kb SRAMs. The implementation results validate our architectural design and the proposed architecture can support real time processing of 1080P@30 fps. The coding efficiency of our adopted method far outperforms (0.57 dB PSNR gain in average) the traditional low-complexity MD (LCMD) methods and the throughput of our designed pipeline is increased by 11.3%, 19% and 17% for I, P and B frames, respectively, compared with the existed RDO-based architecture.

An efficient foreground-based surveillance video coding scheme in low bit-rate compression

Many works have been done in the area of surveillance video compression, while problems still exist. The block-based schemes have blocking artifacts in the edge of foreground, while the object-based coding schemes have excessive bit consumption for coding the object shape. A novel foreground-based (FG-based) coding scheme is presented in this paper to solve these two problems and can gain better video quality at low bit-rate. The improvement comes from: 1) obtaining a foreground frame (FG-frame) by segmentation, in which proper constant value 128 is adopted to represent the luminance and chrominance value of background pixel and thus the residue error is reduced; 2) FG-based motion estimation (ME) and motion compensation (MC), which are more accurate for the foreground prediction and reduce the residue error of edge block in the foreground; 3) a new coding mode (BG-mode) is designed to better code the background when it is falsely segmented as foreground in FG-frames; 4) FG-based rate distortion optimized (RDO) mode decision (MD) is proposed to emphasize the foreground by calculating the distortion in the foreground domain; 5) avoiding shape coding by recovering the shape mask from the reconstructed foreground (REC-FG) frame and the constant background value 128. Our scheme is implemented with AVS encoder platform and the experiment results show the efficiency of the proposed scheme.