Chuang Zhu

Multi-level low-complexity coefficient discarding scheme for video encoder

Rate-Distortion (R-D) optimization technique plays an important role in video coding. R-D sense discarding (thresholding) technique can make great improvement on the coding efficiency. This work first proposes a multi-level coefficient discarding scheme, which is composed of coefficient-level (CL), block-level and macroblock-level discarding. In CL, coefficient-level R-D cost function is formulated and then CL discarding scheme is developed. At last, an effective implementation method is proposed to reduce the complexity of the proposed scheme. The experimental results show that our proposed multi-level discarding scheme can improve the coding performance of video encoder by 0.15db in average.

Fast algorithm of coding unit depth decision for HEVC intra coding

The emerging high efficiency video coding standard (HEVC) achieves significantly better coding efficiency than all existing video coding standards. The quad tree structured coding unit (CU) is adopted in HEVC to improve the compression efficiency, but this causes a very high computational complexity because it exhausts all the combinations of the prediction unit (PU) and transform unit (TU) in every CU attempt. In order to alleviate the computational burden in HEVC intra coding, a fast CU depth decision algorithm is proposed in this paper. The CU texture complexity and the correlation between the current CU and neighbouring CUs are adaptively taken into consideration for the decision of the CU split and the CU depth search range. Experimental results show that the proposed scheme provides 39.3% encoder time savings on average compared to the default encoding scheme in HM-RExt-13.0 with only 0.6% BDBR penalty in coding performance.

Adaptive multi-resolution motion estimation using texture-based search strategies

Motion estimation is the most complex module which contributes nearly 70% of computation resources in a hardware-based video encoder. This huge computational complexity limits the performance of HD video encoders in terms of encoding speed and power consumption. This paper presents a hardware oriented multi-resolution motion estimation algorithm using adaptive search strategies to reduce computational complexity. The spatial homogeneity and the temporal stationarity characteristics of video sequences are adaptively detected to determine search range and down-sampling rate. Homogeneous regions are detected by using Sobel edge operators and stationary regions are detected by using temporal information. These texture-based search strategies make motion estimation more concise under fixed computational complexity constraint. Additional computational cost originated by determining the search strategies can be neglected due to the simple addition and shift operations. Experimental results show that the proposed algorithm achieves better performance and reduces computation cost by 40% compared with previous works.

On a Highly Efficient RDO-Based Mode Decision Pipeline Design for AVS

Rate distortion optimization (RDO) is the best known mode decision method, while the high implementation complexity limits its applications and almost no real-time hardware encoder is truly full-featured RDO based. In this paper, first, a full-featured RDO-based mode decision (MD) algorithm is presented, which makes more modes enter RDO process. Second, the throughput of RDO-based MD pipeline is thoroughly analyzed and modeled. Third, a highly efficient adaptive block-level pipelining architecture of RDO-based MD for AVS video encoder is proposed which can achieve the highest throughput to alleviate the RDO burden. Our design is described in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18- μm CMOS technology with 232 K logic gates and 85 Kb SRAMs. The implementation results validate our architectural design and the proposed architecture can support real time processing of 1080P@30 fps. The coding efficiency of our adopted method far outperforms (0.57 dB PSNR gain in average) the traditional low-complexity MD (LCMD) methods and the throughput of our designed pipeline is increased by 11.3%, 19% and 17% for I, P and B frames, respectively, compared with the existed RDO-based architecture.

A highly efficient pipeline architecture of RDO-based mode decision design for AVS HD video encoder

Like H.264, AVS video coding standard also uses macroblock (MB) based motion compensation (MC) and mode decision (MD). Rate distortion optimization (RDO) is the best known mode decision method, but with a high computational complexity that limits its applications. In our paper, firstly an MD algorithm based on RDO is given, which makes more mode candidates enter into RDO mode decision with little hardware resource increment. We further analyze the pipeline structure in detail, and implement a block-level 5-stage hardware pipeline. It can support the real time RDO mode decision processing of 1080P@30fps, and the coding efficiency is about 0.5db higher than the traditional SAD method. Our design is described in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18-µm CMOS technology with 215K logic gates and 80 KB SRAMs.

An adaptive inter CU depth decision algorithm for HEVC

The emerging High-Efficiency Video Coding (HEVC) standard has introduced a number of new coding tools, such as a quad-tree based coding unit (CU). The quadtree-structured coding unit achieves significant coding efficiency improvements compared to H264/AVC. However, the complexity of CU depth decision associated with Rate-Distortion (R-D) cost computation dramatically increased. In order to alleviate the computational burden in HEVC inter coding, a fast CU depth decision algorithm is proposed in this paper. Firstly, zero CU detection method for HEVC is proposed as early termination algorithm. Secondly, the CU depth pruning strategies are adaptively determined according to standard deviation of statistic spatiotemporal depth information. Finally, when the neighbors are not available or have a very weak correlation, edge gradient of current coding tree unit (CTU) is considered as main factor for CU depth pruning method. Experimental results demonstrate that, compared with the original HM16.0 implementation, the proposed algorithm achieves about 40.5% encoding time saving with ignorable coding performance degradation.

Window-based rate control for video quality optimization with a novel INTER-dependent rate-distortion model

Most model-based rate control schemes use independent rate-distortion (R-D) models at macroblock (MB) level to represent the relationship among bit rate, distortion and encoding complexity. However the correlations between frames (INTER-dependency) are not well considered for distortion, bit allocation and quantization parameter (QP) decision. In this paper, a novel INTER-dependent R-D model is proposed based on the theoretical analysis of the relationship between the predicted residual of one frame and the distortion of its reference frame. To achieve both bit rate accuracy and consistent video quality, a window-based rate control scheme with two sliding windows is introduced. One window is to group certain previously encoded frames and current frame to control the bit rate and buffer delay; the other is to group certain future encoding frames to optimize the fluctuation of video quality. Furthermore, the optimization of Lagrange multiplier is also discussed under the INTER-dependent situation. Experimental results demonstrate that the proposed window-based rate control scheme with INTER-dependent R-D model can achieve accurate target bit rate and improve PSNR performance, meanwhile the variation of PSNR is the smallest compared with other three benchmark algorithms. This one-pass rate control scheme is highly practical for the real-time video coding applications. Proposed a novel INTER-dependent R-D model.Proposed a window-based rate control scheme with two sliding windows to achieve both accurate bit rate and consistent video quality.Optimized the Lagrange multiplier under the INTER-dependent situation.

A hardware-efficient architecture for multi-resolution motion estimation using fully reconfigurable processing element array

Integer motion estimation (IME) for block-based video coding presents a significant challenge in external memory bandwidth, data latency, and circuit area with the increase of coding complexity and video resolution. To conquer these problems, this paper proposes a hardware-efficient VLSI architecture for multi-resolution motion estimation algorithm (MMEA) based on fully reconfigurable processing element (PE) array. On-chip storage and PE array are carefully designed to support parallel computation and hardware resource sharing. In addition, low data latency is obtained by arranging internal logics in parallel according to the data dependency. As a result, our design can support real time processing of 1080P@30fps with 2 reference frames and a search range of 256×192 and it is implemented under SMIC 0.18-µm CMOS technology with 920K logic gates and 192 KB SRAMs. Compared with previous work, our design can achieve the best performance-price rate benefiting from the proposed re-configurable PE array.

Fast mode decision based on RDO for AVS high definition video encoder

In this paper, we propose a fast and effective mode decision (MD) algorithm based on rate distortion optimization (RDO) for AVS high definition video encoder. The fast algorithm is composed of two parts. Firstly, mode preselection based on sum of absolute difference (SAD) is employed to reduce modes for candidate so as to alleviate the dramatic throughout burden. Secondly, we adopt 4-way parallel scanning technique to reduce the cycles of each mode decision based on RDO. Theoretical analysis and experimental results show that the proposed fast algorithm can meet the needs of 720P and 1080P real-time high definition AVS video encoding. Besides, the mode pre-selection algorithm provides a similar performance to the all modes enabled algorithm. And the 4-way parallel technique using negligible extra resources increases the speed of coding bits estimation by 3.4 times than traditional techniques.

An improved adaptive quantization method based on perceptual CU early splitting for HEVC

High Efficiency Video Coding is the latest video coding standard, and it can achieve significant compression performance with numerous coding tools. It supports different quantization parameters for each different coding unit in any depth coding unit. However, the adaptive quantization (AQ) method in current HEVC suffers from the underestimated spatial activity and Lagrange multiplier selection problems. Whats more, no perceptual considering are taken into the AQ model, thus it cannot obtain performance correctly and reasonably. Therefore, in this paper, we first solve the problems existed in current AQ method and then we propose a novel perceptual AQ method (PAQ) based on an adaptive perceptual CU early splitting algorithm to improve performance. Experiments demonstrate that with SSIM (Structure Similarity) as metric, it can achieve more than −9.3% BD-Rate saving with proposed method compared with the HM10.0 encoder, which outperforms than the existed methods.