Kriyang Shah

Recent Subthreshold Design Techniques

Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

A highly sensitive and ultra low‐power forward body biasing circuit to overcome severe process, voltage and temperature variations and extreme voltage scaling

Summary Dynamic voltage scaling is one of the most popular methods used to reduce energy consumption in todays digital electronic systems. However, addressing process, voltage and temperature variations at subthreshold voltages has become an inevitable procedure. Using a variation-sensitive and ultra low-power design, this paper proposed a novel technique capable of sensing and responding to process, voltage and temperature variations as well as dynamic voltage scaling by providing an appropriate forward body bias so that energy-delay product of the whole system was improved. Theoretical analysis for process variation probability, confirmed by post-layout HSPICE (Synopsys, Inc., Mountain View, CA) simulations for an 8-bit pipelined Kogge–Stone adder, showed that the circuit performance was enhanced in severe variations and extreme voltage scaling situation. For this adder, for example, assuming a voltage scaling from 0.8 to 0.3 V and temperature changes of −15 to 75 °C, the proposed technique brought about a seven times less delay variation, whereas energy-delay product improved by 23% compared with a zero body biased adder. Copyright

A very high Q-factor inductor using MEMS technology

This paper presents the design and optimisation of a very high Quality (Q) factor inductor using MEMS technology for 10GHz to 20GHz frequency band. The effects of various parameters of a symmetric inductor structure on the Q-factor and inductance are thoroughly analysed. The inductor has been designed on Silicon-on-Sapphire (SOS) substrate because it offers superior characteristics of low substrate loss due to the high resistivity of the sapphire material and low capacitive coupling to the substrate. It is also been suspended from the substrate in order to reduce the substrate loss and improved the Q factor. Results indicate that a maximum Q factor of 192 for a 1.13nH inductance at 12GHz is achieved after optimising the symmetric inductor.

A fully-on-chip wideband low noise amplifier for radio telescope applications

This paper presents the design and implementation of a fully on-chip wideband LNA using 0.25-micron Silicon-on-Sapphire (SOS) technology for the next-generation radio telescope application, the Square Kilometre Array (SKA), which demands ultra low noise and wideband operation. The proposed LNA design employs a cascaded inductive degeneration architecture with intermediate LC architecture, resulting in a broadband input matching. The LNA is optimised for minimum noise figure (NF) by employing an external gate-source capacitor which is perfectly matched with a high quality factor (Q) inductors. After optimisation, the LNA achieved a NF from 0.56dB to 0.67dB over 1.1GHZ-band with a minimum gain of 14.9dB at a 2.5-V power supply.

Design and Simulation of Film Bulk Acoustic Wave Resonator in Ku-Band

This paper presents the design of a Film Bulk Acoustic Wave Resonators (FBARs) operating in Ku-band. The one-dimensional (1-D) numerical and the three-dimension (3-D) Finite Element Method (FEM) simulation results are analysed and compared. The results show that coupling coefficient (k2eff) up to 6.5% can be obtained with optimised thickness ratio of electrode/piezoelectric layers of operating frequencies greater than 15GHz. The FBARs have areas of 1.69x10-4µm2 and 7.84x10-4µm2 for series resonance frequency of 14.7GHz and 15.9GHz respectively and achieves quality (Q) factor of 300. The designed FBAR filter operating in Ku-band has the centre frequency of 15.5 GHz, the insertion loss of 3.5dB, out-of-band rejection of 13dB and fractional bandwidth of 6.6%.

Design and analysis of film bulk acoustic wave resonator in Ku-band frequency for wireless communication

This paper presents design of a Film Bulk Acoustic Wave Resonators (FBARs) consisting of piezoelectric film, aluminium nitride (AlN) with top and bottom electrodes of ruthenium (Ru). The lumped Butterworth-Van Dyke (BVD) Circuit model is used to investigate the theoretical harmonic response and extraction equivalent circuit of the FBAR. A three-dimensional (3D) Finite Element Method (FEM) is used to evaluate the electro-mechanical performance of the FBAR. The one-dimension (1D) numerical and the 3D FEM simulation results are analysed and compared. The results show that coupling coefficient (k2 eff) up to 7.0% can be obtained with optimised thickness ratio of electrode/piezoelectric layers. A Figure of Merit (FOM) that considers k2 eff and quality (Q) factor is used for comparison. The area of FBAR is 900μm2 and the active filter area size of the FBAR filter is 5400μm2. The FBAR filter is designed for operation in Kuband with centre frequency of 15.5 GHz and fractional bandwidth of 2.6%. The proposed FBAR filter has insertion loss of -2.3dB which will improve the performance of Ku-band transceiver and improve communication range and data rates in Ku-band communication links.

A 2mA-2.5V low phase noise multi-standard VCO

This paper presents the design of a voltage controlled oscillator (VCO) for multi-standard wireless receiver covering Global Standards for Mobile (GSM), Digital Communication Systems (DCS), Personal Communication Systems (PCS), and Universal Mobile Telecommunication System (UMTS) standards. An effective frequency planning scheme that requires the VCO to tune from 3.2GHz to 4.1GHz and generate multiple bands using frequency division is presented. The presented VCO design employs two current mirrors for efficient current control, a specially designed inductor with quality factor (Q) of 111, and multiple noise filtering techniques to reduce flicker noise components. The proposed multi-standard VCO is designed using 0.25µm silicon-on-sapphire (SOS) technology and consumes only 5.18mW power at 4.1GHz operating frequency. The VCO achieves phase noise of −132dBc/Hz and −141dBc/Hz at 1MHz and 3 MHz offsets respectively resulting in figure of merit (FOM) of −197dBc/Hz/mW.

Film Bulk Acoustic Wave Resonator Filter for Ku-Band Applications

The design and analysis of Ku-band ladder-type filters based on film bulk acoustic wave resonator (FBAR) is presented. The proposed FBAR filter has an insertion loss of-3dB, out-of-band rejection of-12dB, centre frequency of 15.5GHz with 3dB bandwidth of 1.0GHz. Based on the characteristics of the FBAR filter, the expected characteristics of FBAR resonators are determined by using the Butterworth Van Dyke (BVD) equivalent circuit.

Design and analysis of a 10GHz LC-VCO using MEMS inductor

This paper presents design and analysis of a 10GHz inductance-capacitance (LC)-Voltage-Controlled Oscillators (VCO) implemented with a very high quality (Q) factor on-chip Micro-Electro-Mechanical Systems (MEMS) inductor using 0.25μm silicon-on-sapphire (SOS) technology. A new symmetric topology of suspended MEMS inductor is proposed to reduce the length of the conductor strip and achieve the lowest series resistance in the metal tracks. This MEMS inductor has been suspended above the high resistivity SOS substrate to minimise the substrate loss and therefore, achieve a very high Q-factor inductor. A maximum Q-factor of 191.99 at 11.7GHz and Q-factor of 189 at 10GHz has been achieved for a 1.13nH symmetric MEMS inductor. The proposed inductor has been integrated with a VCO on the same substrate using the Metal layers in SOS technology removing the need for additional bond wire. The 10GHz LC-VCO has achieved a phase noise of -116.27dBc/Hz and -126.19dBc/Hz at 1MHz and 3MHz of offset frequency, respectively. It consumes 4.725mW of power from 2.5V supply voltage while achieving a Figure of Merit (FOM) of -189.5dBc/Hz.

Analysis of geometric and non-linear programming as optimization algorithms for low power VLSI circuits

In this paper, performance and accuracy of both General Geometric Programming (GGP) and non-linear programming (NLP) algorithms, for optimization of low power VLSI circuits, have been studied and compared. An optimization procedure based on GGP and logical effort method has been proposed and employed for optimization of variety of sequential logic circuits. The results were compared to the NLP algorithm of Sequential Quadratic Programming (SQP). Experiments showed that the GGP algorithm with Logical Effort method exhibits higher precision and acceptable speed compared to NLP algorithms. In fact, GGP is 9 orders of magnitude more accurate but 24× slower than NLP. However, with increasing circuit complexity the GGP does not degrade like NLP. Consequently, for complex circuits GGP is a good substitution for the speed of NLP algorithms and precision of simple LP (Linear Programming) algorithms, like Logical Effort.