Hajime Nakayama

High density substrate for semiconductor packages using newly developed low CTE build-up materials

The substrates of semiconductor packages not only require high wiring density but also the highest reliability of all printed wiring boards (PWBs). The build-up technology is one of the major concerns to raise wiring density because they have microvias for the interconnection such as interstitial via holes (IVHs). We developed new PWB substrates for semiconductor packages with newly developed low CTE build-up materials and high Tg core board. Inorganic fibrous filler and high heat resistance epoxy resin were adopted as the build-up materials. The insulator shows high elastic modulus at high temperature and low coefficient of thermal expansion. In addition, it has enough resin flow that it can fill up inner buried via holes, and maintain substrate flatness, thus allowing finer line fabrication on any area. The substrate has multiple insulation layers having wiring and IVHs on the core board with buried via holes. The substrate passed stringent tests, e.g. wear resistance and interconnection reliability in various connecting patterns. It demonstrates good mounting capability, such as wire bonding and flip chip attachment due to high modulus and less warpage in the high temperature range. In addition, the PWBs show suitable assembly capability for surface mount devices.