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Featured researches published by Yoshiaki Tsubomatsu.


electronic components and technology conference | 1994

Transfer laminate circuit process for fine pitch wiring technology

Yoshiaki Tsubomatsu; Yasunobu Yoshidomi; Hirohito Ohhata; Toshio Yamazaki; Naoki Fukutomi

The transfer laminate circuit (TLC) process is presented which has a vast potential for extending the wiring density of laminated multichip modules (MCM-Ls) to a level of deposited MCMs (MCM-Ds). In this paper, factors affecting the resolution of wiring patterns produced by TLC process are studied and a feasibility of making fine pitch wiring patterns is demonstrated.<<ETX>>


cpmt symposium japan | 2010

Electroless Ni/Pd/Au plating for semiconductor package substrates-effect of gold plating combinations on gold wire bonding reliability

Yoshinori Ejiri; Takehisa Sakurai; Yoshinori Arayama; Yoshiaki Tsubomatsu; Shuuichi Hatakeyama; Shigeharu Arike; Yukihisa Hiroyama; Kiyoshi Hasegawa

In order to investigate the root causes of the good wire bonding reliability in electroless Ni/Pd/Au plating (ENEPIGEG), the wire bonding reliability of the combinations with electrolytic and electroless processes were evaluated. The reliability of ENEPIGEG and electrolytic Ni (SB-Watt)/IGEG were equivalent to that of the conventional electrolytic Ni (SB-Watt)/electrolytic Au and were excellent. The reliability of electrolytic Ni (SB-Watt)/IGEG was higher than that of EN/Electrolytic Au after heat treatment. We found that the grain size of the gold deposit coordinated with the grain size of the underplated Ni deposit with the epitaxial crystal growth. The large grain size of the gold deposit decreased the grain boundary of the gold deposit and reduced the grain boundary diffusion from the underplated metals onto the gold plating. We concluded that the wire bonding reliability after heat treatment depended on the diffusion behavior of the underplated metals and the grain size of the gold deposit.


Archive | 1995

Fabrication process of semiconductor package and semiconductor package

Naoki Fukutomi; Yoshiaki Tsubomatsu; Fumio Inoue; Toshio Yamazaki; Hirohito Ohhata; Shinsuke Hagiwara; Noriyuki Taguchi; Hiroshi Nomura


Archive | 1996

Method of production of semiconductor device

Aizou Kaneda; Masaaki Yasuda; Itsuo Watanabe; Tomohisa Ohta; Fumio Inoue; Yoshiaki Tsubomatsu; Toshio Yamazaki; Hiroto Ohata; Kenzo Takemura; Akira Nagai; Osamu Watanabe; Naoyuki Shiozawa; Kazuyoshi Kojima; Toshiaki Tanaka; Kazunori Yamamoto


Archive | 1992

Fabrication process of wiring board

Naoki Fukutomi; Hajime Nakayama; Yoshiaki Tsubomatsu; Kouichi Kaitou; Yasunobu Yoshidomi; Yoshihiro Takahashi


Archive | 1995

Semiconductor package manufacturing method and semiconductor package

Naoki Fukutomi; Yoshiaki Tsubomatsu; Fumio Inoue; Toshio Yamazaki; Hirohito Ohhata; Shinsuke Hagiwara; Noriyuki Taguchi; Hiroshi Nomura


Archive | 2000

Substrate for holding a chip of semi-conductor package, semi-conductor package, and fabrication process of semi-conductor package

Yoshiki Sota; Koji Miyata; Toshio Yamazaki; Fumio Inoue; Hidehiro Nakamura; Yoshiaki Tsubomatsu; Yasuhiko Awano; Shigeki Ichimura; Masami Yusa; Yorio Iwasaki


Archive | 1994

Wiring board for electrical tests with bumps having polymeric coating

Naoki Fukutomi; Hidehiro Nakamura; Hajime Nakayama; Yoshiaki Tsubomatsu; Masanori Nakamura; Kouichi Kaitou; Atsushi Kuwano; Itsuo Watanabe; Masahiko Itabashi


Archive | 1987

Process for producing high-density wiring board

Akinari Kida; Naoki Fukutomi; Yoshiaki Tsubomatsu; Takuya Yasuoka


Archive | 1996

Semiconductor device, wiring board for mounting semiconductor and method of production of semiconductor device

Aizou Kaneda; Masaaki Yasuda; Itsuo Watanabe; Tomohisa Ohta; Fumio Inoue; Yoshiaki Tsubomatsu; Toshio Yamazaki; Hirohito Ohata; Kenzo Takemura; Akira Nagai; Osamu Watanabe; Naoyuki Shiozawa; Kazuyoshi Kojima; Toshiaki Tanaka; Kazunori Yamamoto

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