Hakchul Jung

Investigation of Frequency Dependent Sensitivity of Noise Figure on Device Parameters in 65 nm CMOS

We have investigated the noise sensitivity of low noise amplifier (LNA) at different frequency. This noise sensitivity analysis provides insights about noise parameters and it is very beneficial for making appropriate design trade-offs. From this work, the circuit designer can choose the adequate noise parameters tolerances.

A concurrent dual-band CMOS low-noise amplifier for ISM-band application

A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 times 460 mum2.

Design optimization of a 10 GHz low noise amplifier with gate drain capacitance consideration in 65 nm CMOS technology

Most of papers have ignored the effect of gate-drain capacitance of transistor due to its complexity when they analyze a low noise amplifier circuit (LNA). However, as scaling down the CMOS technology, the ratio of gate-drain capacitance (Cgd) to gate-source capacitance (Cgs) increases. This phenomenon affects the input matching, power gain and noise figure of the LNA circuit. In this paper, we propose the circuit analysis with new analytic equations derived from equivalent circuit of LNA which considered the Cgd effect. With this approach, the input power matching, overall trans-conductance and noise figure could be accurately calculated more than conventional equation. Moreover, a design approach is introduced to optimize the LNA circuit. Prior to fabrication of full LNA circuit, optimum bias and width could be determined to maximize FoM. This paper shows the guide line to design an LNA circuit at 10 GHz operating frequency using 65 nm technology.

A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology

In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inductively degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P-1dBin) and power consumption. In low power design, above all things proper power gain and low power consumption should be attained. This limitation makes ultra low power LNA optimization different from ordinary one. We analyze each performance factor in low power design and optimize figure of merit (FoM) with some specification goal.

MOS varactor modeling for mm-Wave applications

A RF MOS varactor model has been verified in mm-wave range in this paper. Since this non linear model consisted of the SPICE compatible lumped elements with physical meanings has a single topology and simple equations, it can be easily implemented in commercial circuit simulators. Based on the S-parameter measurement, the efficient and accurate parameter extraction methodology from analysis for Z-parameters on this equivalent circuit was developed and successfully validated up to 110 GHz.

Analytic approach to power-constrained CMOS low-noise amplifier design with figure of merit consideration

In this paper, design approach for a 5.8-GHz power-constrained CMOS low-noise amplifier using 0.13-mum process technology is presented. To evaluate the overall performance of an LNA, figure of merit (FoM) is adopted. Figure of merit includes power gain, noise figure, power dissipation and the operation frequency. Each performance factor of FoM is analytically expressed in device parameters. We show that FoM is maximized by optimizing the transistor size and bias condition. Effect of the external capacitance between the gate and the source of the input transistor for power-constrained design is explained and its influence on FoM is also discussed.