Halil Kiper

Digital Approaches to ISI-Mitigation in High-Resolution Oversampled Multi-Level D/A Converters

A new digital signal processing approach to shaping intersymbol interference (ISI) and static mismatch errors simultaneously in oversampled multi-level digital to analog converters (DAC) has recently been proposed. In this paper, a mathematical framework is established for analyzing ISI errors as well as comparing the ISI sensitivities of different mismatch shaping algorithms. The framework is used to analyze the fundamental problems of popularly used algorithms such as data-weighted-averaging (DWA) in the presence of nonlinear ISI: Large-signal even-order distortion and frequency modulated harmonics at low signal levels. The new ISI-shaping algorithm results in significant improvement over previous schemes including the modified Mismatch Shaper (MMS) which also addresses ISI error. The new ISI shaper, while increasing the digital complexity, practically eliminates the need for conventional ISI mitigation techniques such as time consuming, layout-critical, non-automated and process specific analog design methods. The advantages of ISI shaping is further verified on an experimental audio DAC with simple non-return-to-zero (NRZ) current steering segments implemented in a 45 nm CMOS process and running off a single-phase clock of only 3.072 MHz.

A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS

Mobile consumer audio applications are demanding higher performance, longer battery life and lower cost. Achieving low out-of-band noise (OBN) is one of the key elements in designing inexpensive, low-power and robust audio DACs. Lowering OBN reduces the sensitivity to circuit mismatch, glitch energy and clock jitter. The need for an expensive analog post filter that requires high bias currents can be eliminated altogether. Requirements on the application clock are relaxed and low-cost PLLs can be used in the system. To reduce OBN, one needs to increase modulator resolution. The popular method is to increase the number of unit weighted elements in an oversampled DAC. This results in high digital complexity, inter-symbol-interference (ISI) and tonal problems when shaping mismatch errors. Reported multi-bit oversampling audio DACs [1, 2] use noise-shaped segmentation to split a main modulator output into binary weighted sub-DACs. This segmentation increases the resolution that can be used in the main modulator with relatively simple digital signal processing to shape mismatch errors outside the audio band.

A 108dB-DR 120dB-THD and 0.5V rms output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS

The current trend in high-performance audio DACs is to use fine-resolution quantization to reduce the out-of-band noise (OBN), reduce jitter sensitivity, and simplify analog filtering. Recent techniques achieve this goal by using a mix of DAC elements with different weights, e.g., segmenting [1] or cascading [2]. Unlike 1b modulation, the multi-level DACs need mismatch shaping algorithms to compensate for the typical 0.1 to 1% on-die mismatch. In addition to the element mismatch, dynamic error sources such as asymmetrical switching, clock skew, and parasitic memory are major hindrances to achieve distortion and dynamic range targets. The resulting dependence of present symbol error to the past symbol is referred to as inter-symbol-interference (ISI), and is a function of the switching activity of all the individual DAC elements. Unfortunately, the popular mismatch-shaping algorithms (e.g., rotation-DWA) are addressing only the static mismatch problem. They typically increase the switching activity thus amplify ISI errors. Furthermore, the error comes often in the form of spurious tones with signal-dependent frequency (FM modulation [3]) that ruins the low-amplitude performance (harmonics for a −60dB signal) which is critical for the perceived sound quality. A common remedy is to add a digital DC offset to shift the tones out of band. However, this merely moves the problematic amplitude region, and does not solve the problem. Moreover, ISI errors often limit the large signal THD as a result of a strong signal-dependent modulation of the element transition rate.

A 28mW WCDMA/GSM/GPRS/EDGE transformer-based receiver in 45nm CMOS

A transformer-based receiver designed in 45nm CMOS that meets WCDMA, GSM, GPRS, and EDGE system requirements is presented. The receiver requires no interstage SAW filters and consumes 20mA from 1.4V. The use of a transformer at the LNA output helps achieve high linearity by lowering the voltage swing while simultaneously providing current gain. The analog back end is implemented with two cascaded gain stages and a 2nd order ΣΔ ADC. The receiver has a gain of 60dB, noise figure of 3.0dB and an IIP2 of ≫+50dBm on both I+Q channels. The die area is 1.35mm2 for 4 bands.