Rahmi Hezar

Digital Approaches to ISI-Mitigation in High-Resolution Oversampled Multi-Level D/A Converters

A new digital signal processing approach to shaping intersymbol interference (ISI) and static mismatch errors simultaneously in oversampled multi-level digital to analog converters (DAC) has recently been proposed. In this paper, a mathematical framework is established for analyzing ISI errors as well as comparing the ISI sensitivities of different mismatch shaping algorithms. The framework is used to analyze the fundamental problems of popularly used algorithms such as data-weighted-averaging (DWA) in the presence of nonlinear ISI: Large-signal even-order distortion and frequency modulated harmonics at low signal levels. The new ISI-shaping algorithm results in significant improvement over previous schemes including the modified Mismatch Shaper (MMS) which also addresses ISI error. The new ISI shaper, while increasing the digital complexity, practically eliminates the need for conventional ISI mitigation techniques such as time consuming, layout-critical, non-automated and process specific analog design methods. The advantages of ISI shaping is further verified on an experimental audio DAC with simple non-return-to-zero (NRZ) current steering segments implemented in a 45 nm CMOS process and running off a single-phase clock of only 3.072 MHz.

A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners

In this paper, we present a 25 dBm Class-D outphasing power amplifier (PA) with cross-bridge combiners. The Class-D PA is designed in a standard 45 nm process while the combiner is implemented on board using lumped elements for flexibilities in testing. Comparing with conventional non-isolated combiners, the elements of the cross-bridge combiner are carefully chosen so that additional resonance network is formed to reduce out-of-phase current, thereby increasing backoff efficiency of the outphasing PA. The Class-D outphasing PA with the proposed combiner is manufactured and measured at both 900 MHz and 2.4 GHz. It achieves 55% peak power-added efficiency (PAE) at 900 MHz and 45% at 2.4 GHz for a single tone input. For a 10 MHz LTE signal with 6 dB PAR, the PAE is 32% at 900 MHz with -39 dBc adjacent channel power ratio (ACPR) and 22% at 2.4 GHz with -33 dBc ACPR. With digital predistortion (DPD), the linearity of the PA at 2.4 GHz is improved further to reach -53 dBc, -50 dBc, -42 dBc ACPR for 10 MHz, 20 MHz, and 2-carrier 20 MHz LTE signals.

A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS

Mobile consumer audio applications are demanding higher performance, longer battery life and lower cost. Achieving low out-of-band noise (OBN) is one of the key elements in designing inexpensive, low-power and robust audio DACs. Lowering OBN reduces the sensitivity to circuit mismatch, glitch energy and clock jitter. The need for an expensive analog post filter that requires high bias currents can be eliminated altogether. Requirements on the application clock are relaxed and low-cost PLLs can be used in the system. To reduce OBN, one needs to increase modulator resolution. The popular method is to increase the number of unit weighted elements in an oversampled DAC. This results in high digital complexity, inter-symbol-interference (ISI) and tonal problems when shaping mismatch errors. Reported multi-bit oversampling audio DACs [1, 2] use noise-shaped segmentation to split a main modulator output into binary weighted sub-DACs. This segmentation increases the resolution that can be used in the main modulator with relatively simple digital signal processing to shape mismatch errors outside the audio band.

A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications

In this paper, we present a 23 dBm PWM based fully digital transmitter designed in standard 45 nm CMOS process. The digital transmitter utilizes sigma-delta modulation and pulse-width modulation to convert high resolution baseband I and Q signals into 3-level switching signals, thereby allowing efficient Class-D PA stages to be used. In addition, cascaded sigma-delta stages and switched-capacitor combining are incorporated into the architecture to significantly reduce the out-of-band quantization noise while maintaining excellent efficiency. The proposed transmitter is fully digital from baseband to RF and can be used to replace the entire analog/RF signal chain in a traditional transmitter. It achieves peak output power of 23 dBm with 47% power-added efficiency (PAE). For an 20 MHz OFDM signal with 8.2 dB peak-to-average power ratio (PAR), the PAE is 23%. The linearity of the digital transmitter meets WiFi spectral mask without any digital predistortion.

A 4/sup th/-order 86dB CT /spl Delta//spl Sigma/ ADC with two amplifiers in 90nm CMOS

A fourth-order 1b CT /spl Delta//spl Sigma/ converter using a two-amplifier loop and a 267MHz sampling frequency is implemented in 90nm CMOS. A double-loop architecture couples passive poles with a reduced number of active blocks to improve area and power while achieving 86dB peak SNR over a 600kHz band.

A 23dBm fully digital transmitter using ΣΔ and pulse-width modulation for LTE and WLAN applications in 45nm CMOS

This paper presents a 23 dBm fully digital transmitter designed in a standard 45 nm CMOS process. The digital transmitter replaces the entire analog/RF signal chain in a traditional transmitter architecture. It utilizes ΣΔ modulation and pulse-width modulation to turn high resolution baseband I and Q signals into switching signals, thereby allowing efficient Class-D PA stages to be used. In addition, cascaded ΣΔ stages and switched-capacitor combining are incorporated into the architecture to reduced out-of-band quantization noise while maintaining good efficiency. The proposed transmitter achieves peak output power of 23 dBm with 47% power added efficiency (PAE). For a OFDM signal with 8.2 dB peak-to-average power ratio (PAR), the PAE is 23%. The linearity of the digital transmitter meets WiFi spectral mask without any digital predistortion.

High efficiency multi-mode outphasing RF power amplifier in 45nm CMOS

A high efficiency multi-mode class-E outphasing RF power amplifier with a passive combining circuit is presented. The multi-mode PA improves efficiency at lower power levels by switching ON and OFF individual branches and using Efficiency Enhancement Circuit (EEC). The proposed power amplifier is designed in 45nm CMOS technology. The PA delivers 31.6 dBm peak output power at 2.4GHz with 49.2% drain efficiency in high power single level mode. For 64-QAM LTE signal with 10MHz and 20MHz bandwidth, -57 dBc and -53 dBc ACPR are obtained in single level outphasing mode with DPD. 25% and 33% average drain efficiency are obtained with LTE signal with 6 dB peak-to-average power ratio (PAPR) in single level outphasing and AMO mode respectively.

A 25 dBm outphasing power amplifier with novel non-isolated combining network

This paper presents a 25 dBm outphasing power amplifier designed in a standard 45 nm CMOS process. Instead of using bulky quarter-wave transmission lines or transformers as non-isolated combiners, we propose a new combiner based on lump elements. The elements of the combiner act differently for in-phase and out-of-phase components, which allows additional resonant networks to be formed for improved backoff efficiency. The proposed PA design achieves 55% peak power added efficiency (PAE) at 900 MHz and 45% at 2.4 GHz. For an OFDM signal with 6 dB PAR, the PAE is 32% at 900 MHz and 22% at 2.4 GHz. The linearity of the PA meets WiFi spec without digital predistortion (DPD). With DPD, the linearity of the PA can be improved further to reach -53 dBc, -50 dBc, -42 dBc ACPR for 10 MHz, 20 MHz, and 2-carrier 20 MHz LTE signals.

A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS

A high efficiency class-E outphasing RF power amplifier is presented using a new passive combining circuit. A Power Enhancement Circuit (PEC) and an Efficiency Enhancement Circuit (EEC) are also proposed as part of the combiner that increase output power without violating reliability limits and improve efficiency at power back-off, respectively. The proposed power amplifier is designed in 45nm CMOS technology. Simulation results and measurement data are presented to demonstrate the performance of the proposed PA. The PA delivers 29.5 dBm peak output power at 2.4GHz with 46.76% drain efficiency at peak output power, 32.96% drain efficiency at 3 dB power back-off and 21.16% drain efficiency at 6 dB power back-off. Better than -50 dBc ACPR is obtained with 64-QAM LTE signal with 10MHz and 20MHz bandwidth. 21% average efficiency is obtained with LTE signal with 6 dB peak-to-average power ratio (PAPR).

Modeling and predistortion for digital transmitters based on delta-sigma and pulse-width modulation

Digital transmitters based on delta-sigma modulation (DSM) and pulse-width modulation (PWM) are very active research areas because of their potential for achieving better integrated, lower cost, and higher efficiency communication devices. To achieve the best output power and efficiency, it is critical to have accurate models of the nonlinear behaviors in these transmitters and the ability to apply nonlinearity compensation. Previous research efforts have been mostly focused on behavior modeling of this type of transmitters using bit sequences from the DSM/PWM. The resulting models have high complexity and computation cost. In this paper, we start from the passband Volterra model and derive a new baseband Volterra model for this type of transmitters. The effectiveness of the new model is demonstrated in simulations and in linearizing of a 45nm CMOS digital transmitter. For a 10 MHz LTE signal, DPD based on the new model achieved around 5 dB adjacent channel power ratio improvement, while DPD based on conventional models showed improvement less than 1 dB.