Hamed Elsimary

Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm

This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.

High-performance, low-power architecture for scalable radix 2 montgomery modular multiplication algorithm

This paper presents a new processor array architecture for scalable radix 2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by C. Koc. Also, the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance-in terms of area and speed-and lower power consumption than the previous architecture extracted by Ç. Koç.

New and improved word-based unified and scalable architecture for radix 2 Montgomery modular multiplication algorithm

This paper presents a new and improved word-based processor array architecture for unified and scalable radix2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by Ç. Koç̧, and also the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. Moreover, this architecture was modified to reduce the critical path delay and area by replacing the two levels of carry save adder (CSA) logic by modified 4-to-2 CSA that use only one level of dual field adder logic (DFA) taking advantage of processing two operand words by the same processing element (PE) of the processor array. An ASIC Implementation of the proposed architecture shows that it can perform 1024-bit modular multiplication (for word size w = 32) in about 17.07 μs. Also, the results show that it has smaller Area ×Time values compared to all existing designs by ratios ranging from 11.6 % to 47.8 % which makes it suitable for implementations where both area and performance are of concern. Moreover, it has higher throughput (1.8-39.5 %) than most of the published unified and scalable architectures except the architecture extracted by Harris. It has slightly higher throughput (4.5 %) than the proposed one.

New processor array architecture for scalable radix 2 Montgomery modular multiplication algorithm

This paper presents a new processor array architecture for scalable radix2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by Ç . Koç, and also the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance - in terms of area and speed - than the previous architecture extracted by Ç. Koç.

Encoding true-color images with a limited palette via soft vector clustering as an instance of dithering multidimensional signals

One of the classic problems of digital image processing is to encode true-color images for the optimal viewing on displays with a limited set of colors. A major manifestation of optimal viewing in this regard is to maximally remove parasitic artifacts in the degraded encoded images such as the contouring effect. Several robust attempts have been made to solve this problem over the past 50years, and the first contribution of this paper is to introduce a simple - yet effective - novel solution that is based on soft vector clustering. The other contribution of this paper is to propose the application of the soft clustering methodology deployed in our color-encoding solution for the dithering of multidimensional signals. Dithering essentially adds controlled noise to the analog signal upon its digitization so that the resulting quantization noise is dispersed over a much wider band of the frequency domain and is therefore less perceptible in the digitized signal. This comes of course at the price of more overall quantization noise. Dithering is a vital operation that is performed via well-known simple schemes upon the analog-to-digital conversion of one-dimensional signals; however, the published literature is still missing a general neat scheme for the dithering of multidimensional signals that is able to handle arbitrary dimensionality, arbitrary number and distribution of quantization centroids, and with computable and controllable noise power. This gap is also filled by this paper.