Hamid Azimi

Fatigue crack propagation along polymer-metal interfaces in microelectronic packages

In this study, a fracture mechanics-based technique was used for characterizing fatigue crack propagation (FCP) at polymer-metal interfaces. Sandwich double-cantilever beam (DCB) specimens were fabricated using nickel and copper-coated copper substrates bonded with a thin layer of silica-filled polymer encapsulant. Under cyclic loading, crack propagation was found to occur at the polymer-metal interface. The interfacial failure mode was verified by scanning electron microscopy (SEM) analysis of the fatigue fracture surfaces. The crack growth rate was found to have a power-law dependence on the strain energy release rate range, and exhibited a crack growth threshold, much like the fatigue crack growth threshold stress intensity factor range for monolithic bulk metals, polymers, and ceramics. Interfacial FCP data for three candidate encapsulants predicted cracking resistances that were well correlated with package-level reliability tests. By varying the surface roughness of the copper and nickel plating, it was shown that interfacial FCP resistance increased with increasing roughness. The observed increases in FCP resistance were attributed to a reduction in the effective driving force for fatigue fracture along the rougher interfaces, and could be accounted for by a crack-deflection model.

Flip chip pin grid array (FC-PGA) packaging technology

As microelectronics moves toward greater levels of integration, functionality and performance, packaging technology complexity grows in direct proportion. With Si process evolution to finer feature sizes, microprocessor designs are achieving higher system clock speeds. As a result, the level of integration and interconnect density between processor chips and substrate has increased tremendously. This brings an array of challenges for package design, substrate technology and assembly process development. For highly integrated packaging at competitive cost, the flip chip pin grid array package (FC-PGA) is proposed as an innovative socketable solution which includes use of laser drilled blind/buried vias on PTH and SMT pins to ease routing and alleviate loop inductance. Use of an existing PGA socket infrastructure expedites OEM acceptance of the new package design in various configurations. This paper describes key features of FC-PGA and technical challenges encountered in FC-PGA design/validation and packaging process development, such as solder composition selection, SMT pin technology optimization, and resolution of via delamination and flip chip solder bump nonwetting problems. FC-PGA package design and process development efforts have demonstrated the feasibility of high density flip chip interconnect on organic substrates and high speed bus functionality with low cost, high yield, manufacturable and reliable packaging solutions, which have been utilized in Pentium/sup TM/ III microprocessors.