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Javier Soto Gonzalez

Intel

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Publication

Featured researches published by Javier Soto Gonzalez.

Archive | 2009

Semiconductor package with embedded die and its methods of fabrication

John S. Guzek; Javier Soto Gonzalez; Nicholas R. Watts; Ravi K. Nalla

Archive | 2010

MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALLY EMBEDDED DIE AND A PROCESS OF FORMING THE SAME

Javier Soto Gonzalez; Houssam Jomaa

Archive | 2011

Forming functionalized carrier structures with coreless packages

Ravi K. Nalla; John S. Guzek; Javier Soto Gonzalez; Drew W. Delaney; Hamid Azimi

Archive | 2013

Substrate with embedded stacked through-silicon via die

Javier Soto Gonzalez; Houssam Jomaa

Archive | 2008

Coreless substrate package with symmetric external dielectric layers

Javier Soto Gonzalez; Tao Wu; Pallavi Alur; Mihir Roy; Sheng Li; Reynaldo Olmedo

Archive | 2014

Multichip integration with through silicon via (TSV) die embedded in package

Digvijay A. Raorane; Yonggang Li; Rahul N. Manepalli; Javier Soto Gonzalez

Archive | 2013

Forming die backside coating structures with coreless packages

Rahul N. Manepalli; Mohit Mamodia; David Q. Xu; Javier Soto Gonzalez; Edward R. Prack

Archive | 2014

Panel level fabrication of package substrates with integrated stiffeners

Robert Starkston; John S. Guzek; Patrick Nardi; Keith Jones; Javier Soto Gonzalez

Archive | 2016

METHODS OF FORMING SENSOR INTEGRATED PACKAGES AND STRUCTURES FORMED THEREBY

Kyu Oh Lee; Zheng Zhou; Islam A. Salama; Feras Eid; Sasha N. Oster; Lay Wai Kong; Javier Soto Gonzalez

Archive | 2015

PROCESSES OF MAKING PAD-LESS INTERCONNECT FOR ELECTRICAL CORELESS SUBSTRATE

Javier Soto Gonzalez; Charavana K. Gurumurthy; Robert Nickerson; Debendra Mallik

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John S. Guzek

Intel

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Ravi K. Nalla

Intel

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Drew W. Delaney

Intel

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Hamid Azimi

Intel

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Houssam Jomaa

Intel

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Charavana K. Gurumurthy

Intel

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Debendra Mallik

Intel

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Rahul N. Manepalli

Intel

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Robert Nickerson

Intel

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David Q. Xu

Intel

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