Hamidreza Ahmadian

End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips

Mixed-criticality systems combine applications at different levels of criticality on the same platform. Today, mixed-criticality integration is addressed individually at different integration levels such as the operating system, the chip-level and the cluster-level. Since many mixed-criticality systems span all of these integration levels, a system perspective of mixed-criticality applications is required. The access to remote resources located on another chip needs to be relayed via gateways involving gateways between on-chip and off-chip networks (i.e., vertical integration) and gateways between different types of off-chip networks (i.e., horizontal integration). This paper introduces a system model with gateways for end-to-end channels over hierarchical, heterogeneous and mixed-criticality networks. We focus on the timing of end-to-end channels, as well as the interoperability across gateways.

Time-Triggered Extension Layer for On-Chip Network Interfaces in Mixed-Criticality Systems

The increasing trend towards mixed-criticality in different domains demands a platform in which the physical integration of subsystems with different criticalities is accommodated. A fundamental prerequisite for such a platform is to establish temporal and spatial segregation between different subsystems in order to eliminate the interference on safety-critical functions, caused by non-safety-critical ones. Furthermore, as mixed-criticality systems often comprise heterogeneous subsystems, the platform shall support different timing models (e.g., periodic and sporadic activities). This paper introduces an extension layer for the Network Interface (NI) of a network-on-a-chip in order to establish the temporal and spatial partitioning over the entire chip. We describe how chip-wide temporally aligned activities of different NIs in combination with resource allocations assure the absence of interference for time-triggered messages and bounded latencies for rate-constrained messages. The chip-wide configuration of the NIs establishes guarding windows for time-triggered messages and traffic shaping of rate-constrained messages.

Scheduling and allocation of time-triggered and event-triggered services for multi-core processors with networks-on-a-chip

Multi-core processors are gaining increasing importance in safety-relevant embedded real-time systems, where temporal guarantees must be ensured despite the sharing of on-chip resources such as processor cores and networks-on-a-chip. At the same time, many applications comprise workloads with different timing models including time-triggered and even-triggered communication. This paper introduces a scheduling model based on Mixed Integer Linear Programming (MILP) supporting the allocation of computational jobs to processing cores as well as the scheduling of messages and the selection of paths on networks-on-a-chip. The model supports dependencies between computational jobs and it combines both time-triggered and event-triggered messages. Phase-alignment of time-triggered messages is performed, while avoiding collisions between time-triggered messages and satisfying bandwidth constraints for event-triggered messages. Example scenarios are solved optimally using the IBM CPLEX optimizer yielding minimal computational and communication latencies.

A Realistic Approach to a Network-on-Chip Cross-Domain Pattern

The transition from conventional federated architectures to integrated architectures enables the integration of functionalities with different criticality (such as safety, security and real-time) on a single embedded computing platform. Many embedded systems require distributed subsystems with networks (e.g., EtherCAT or Ethernet) to satisfy computational resource demands and installation requirements and ensure fault-tolerance. The broad trend of the integration of functionalities with different criticality on a single embedded computing platform involves the implementation of safe and predictable communication systems with temporal segregation between different criticality. However, they represent challenges of certification such as the guarantee of non-interference between safety-critical and non-safety-critical communications, which leads to the increase of engineering and certification cost. This paper contributes a network-on-chip cross-domain pattern which provides a generic solution to recurring problems in mixed-criticality networks. In addition, this paper presents a modular safety case for an IEC 61508 compliant mixed-criticality network that is used for defining the linking analysis of the proposed network pattern. On the other hand, this paper also defines the integration of the cross-domain pattern on a simplified wind turbine case study.

Co-simulation framework for AUTOSAR multi-core processors with message-based Network-on-Chips

Simulation environments play a very important role in the development of embedded systems helping system architects in exploring design decisions. However, the simulation of AUTOSAR multi-core processors with Network-on-Chips (NoCs) for inter-core communication is still a significant research problem. Message-based NoCs provide significant advantages for real-time embedded systems as in the case of the automobile industry. Such a simulation would provide early insights into the real-time behavior of the AUTOSAR application on the message-based multi-core chip. This paper presents as a novel contribution a co-simulation framework supporting the integration of the AUTOSAR architecture with NoC-based platforms. We describe a simulation model for application cores playing the role of virtual AUTOSAR ECUs on the MPSoC platform. The framework introduces an interface for the co-simulation of simulation models for the AUTOSAR-based software (virtual ECUs), the natural environment and the NoC behavior. This co-simulation interface combines a Functional Mock-up Unit (FMU) and a local coordinator for the synchronization and the data exchange between the simulators hosting the simulation models. The implementation is performed using the VEOS simulator for the AUTOSAR-based software and physical environment models, and the GEM5 simulator for the on-chip communication level. An anti-lock braking use case serves for the evaluation of the co-simulation framework.1

Time-Triggered and Rate-Constrained On-chip Communication in Mixed-Criticality Systems

The ongoing trend to integrate multiple functions with different criticalities on a single platform calls for a robust on-chip communication infrastructure in which subsystems of different criticalities can coexist and interact. A fundamental prerequisite for such a platform is to eliminate any interference between safety-critical functions and non safety-critical ones. Furthermore, as mixed-criticality systems often comprise heterogeneous subsystems, the platform shall support different timing models (e.g., periodic and sporadic activities). This paper introduces an extension layer for the Network Interface (NI) of a network-on-a-chip in order to establish temporal and spatial partitioning over the entire chip. We describe how chip-wide segregation between different subsystems assures the absence of interference for time-triggered messages and bounded latencies for rate-constrained messages. The configuration of the NIs establishes guarding windows for time-triggered messages and traffic shaping of rate-constrained messages.

Fault recovery and adaptation in time-triggered Networks-on-Chips for mixed-criticality systems

Adaptivity in terms of fault recovery and energy efficiency alongside with mixed-criticality support are demanded in todays embedded systems. Safety-critical systems are desired to switch between precomputed resource allocations at runtime based on the monitored information from the platform. In addition, those systems are desired to adjust their internal behavior with regard to a change in the environment, while operating at a desired safety level. At the same time, resource requests in such systems can be highly dynamic and data dependent. Aiming at meeting a superset of all worst case demands leads to unaffordable overheads in terms of resource utilization. Hence, efficient resource management mechanisms are required to provide fault recovery and to make the system adaptive to the changes in the environmental or the resource requests, while keeping the system at a safe state. This paper introduces a solution for supporting resource management in networks-on-chips that fulfills the requirements of adaptive mixed-criticality systems and proposes an architecture that establishes fault recovery by switching between precomputed resource allocations based on the statistical and diagnostic information.

Reusable generic design patterns for mixed-criticality systems based on DREAMS

Abstract Multi-core mixed-criticality systems are complex solutions that provide benefits regarding lower power consumption, size, weight and cost and better performance and scalability, compared with single-core architectures. However, these systems where virtualization mechanisms such as hypervisors are used for integrating functionalities with different criticality levels into the same hardware platform and where on-chip and off-chip communication systems are implemented for communicating, imply certification challenges due to their complexity. Those challenges to certification are supported by the fact that today’s safety-related standard focus on single computing systems where spatial and temporal interferences are quite probable. Multi-core architectures enable sharing resources (e.g., cache memory, I/Os) between more than one processor at the same time, facilitating the appearance of interferences which may hinder the achievement of the spatial and temporal independences. This paper analyses the certification challenges in mixed-criticality systems and identifies some reusable generic solutions to overcome those challenges. The solutions presented in this paper are integrated into a safety wind turbine system that follows the design style introduced in European project DREAMS.

Routing in wireless ad hoc and sensor network underground with sensor data in real-time

This paper first describes the innovative topology and structure of a wireless ad hoc and sensor network in a so called line-in-the-underground formation and the feasibility of achieving a reliable wireless connection underground with regards to a borehole telemetry system. It further describes a routing algorithm/protocol implementation based on a modification of the ad hoc on-demand distance vector protocol to achieve a reliable underground communication scheme for the wireless ad hoc network deployed underground for sensor data acquisition in real time as applied in the borehole telemetry system. Simulations and experiments are conducted to investigate and verify the effectiveness of this routing technique and the performance results are shown.