Mohammed Abuteir

End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips

Mixed-criticality systems combine applications at different levels of criticality on the same platform. Today, mixed-criticality integration is addressed individually at different integration levels such as the operating system, the chip-level and the cluster-level. Since many mixed-criticality systems span all of these integration levels, a system perspective of mixed-criticality applications is required. The access to remote resources located on another chip needs to be relayed via gateways involving gateways between on-chip and off-chip networks (i.e., vertical integration) and gateways between different types of off-chip networks (i.e., horizontal integration). This paper introduces a system model with gateways for end-to-end channels over hierarchical, heterogeneous and mixed-criticality networks. We focus on the timing of end-to-end channels, as well as the interoperability across gateways.

Simulation environment for Time-Triggered Ethernet

Time-Triggered Ethernet (TTEthernet) is an SAE standard of a real-time Ethernet extension, which supports real-time requirements, fault isolation and mixed criticality applications. TTEthernet supports different communication mechanisms ranging from best-effort messaging with a high channel utilization to predictable real-time messaging based on a time-triggered communication schedule. This paper presents a simulation framework for TTEthernet-based systems, which supports the analysis and validation of TTEthernet-based applications at early development stages. We introduce generic model building blocks (e.g., TTEthernet switches, TTEthernet end systems, fault injectors), which can be instantiated, configured and extended to model distributed embedded applications. In particular, these building blocks can be configured to support application-specific time-triggered schedules and communication topologies. The fault injector allows to evaluate the reliability in the presence of messages failures with given failure modes and failure rates. We demonstrate the simulation environment in an example scenario with two TTEthernet switches, multiple end systems and injected faults.

On-chip networks for mixed-criticality systems

We propose the integration of a network-on-chip-based MPSoC in mixed-criticality systems, i.e. systems running applications with different criticality levels in terms of completing their execution within predefined time limits. An MPSoC contains tiles that can be either CPUs or memories, and we connect them with an instance of a customizable point-to-point interconnect from STMicroelectronics called STNoC. We explore whether the on-chip network capacity is sufficient for meeting the deadlines of external high critical workloads, and at the same time for serving less critical workloads that are generated internally. To evaluate the on-chip network we vary its configuration parameters, such as the link-width, and the Quality-of-Service (QoS), in specific the number (1 or 2) and type (high or low priority) of virtual channels (VCs), and the relative priority of packets from different flows sharing the same VC.

Predictable and reliable time triggered platform for Ambient Assisted Living

Todays Ambient Assisted Living (AAL) architectures do not support the real-time and reliability requirements of medical monitoring and closed-loop control applications. Fault-tolerant embedded system architectures, on the other hand, do not address the openness required for the dynamic integration of AAL components. This paper present an AAL architecture based on Time-Triggered Ethernet with support for openness, real-time support and reliability. The starting point is a static allocation of communication slots to end-systems. Based on this static schedule, we perform a dynamic allocation of communication resources to the components within an end-system. Each end-system can host multiple components and the communication of these components is dynamically mapped to parts of the end-systems slot. For this purpose, admission control and resource management services are introduced that ensure temporal and spatial partitioning within end-systems. The architecture is evaluated in a simulation environment based on a medical use case.

Scheduling of rate-constrained and time-triggered traffic in multi-cluster TTEthernet systems

Multi-cluster systems with real-time networks are gaining increasing importance to address the communication needs of large-scale embedded systems in different domains such as automotive, factory automation and health-care systems. At the same time, heterogeneous application subsystems with varying criticality levels require different timing models including time-triggered communication, event-triggered communication with rate-constraints and best-effort communication. An example is the coexistence of periodic control functions, event-triggered comfort functions and streaming multimedia services of in-vehicle electronic systems. This paper presents a scheduling algorithm as well as a simulation and verification framework for such multi-cluster systems. We support the allocation and scheduling of time-triggered and rate-constrained services to processing elements and communication links of multiple Time-Triggered Ethernet (TTE) clusters. The simulation and verification framework supports the automatic generation of test cases based on generic scenario parameters including the connectivity degree as well as the number of clusters, processing elements, switches and services. Thereby, we enable a comprehensive evaluation of the scheduling algorithm for use cases of varying complexity. In addition, the simulation and verification framework is a foundation for the systematic comparison of different scheduling algorithms including the evaluation of schedulability and runtime for different types of scenarios.

Mixed-criticality systems based on time-triggered ethernet with multiple ring topologies

TTEthernet ensures a predictable timing with bounded latency and jitter based on time-triggered and rate-constrained messages. Fault-tolerance using redundant switches and multiple stars is supported to preserve the communication services despite the failure of individual physical links or switches. However, other communication topologies are required in order to achieve scalability to large-scale systems and to support mixed-criticality systems. This paper introduces multi-ring topologies with corresponding TTEthernet switches for large-scale mixed-criticality systems. The architecture supports redundant channels using heterogeneous paths for time-triggered and rate-constrained messages, where switches autonomously perform the duplication and deduplication of redundant messages. Differences with respect to latencies on the redundant paths are hidden to ensure an unchanged network timing in case of failures. The architecture and the proposed switches are evaluated using a simulation framework.

Time-Triggered and Rate-Constrained On-chip Communication in Mixed-Criticality Systems

The ongoing trend to integrate multiple functions with different criticalities on a single platform calls for a robust on-chip communication infrastructure in which subsystems of different criticalities can coexist and interact. A fundamental prerequisite for such a platform is to eliminate any interference between safety-critical functions and non safety-critical ones. Furthermore, as mixed-criticality systems often comprise heterogeneous subsystems, the platform shall support different timing models (e.g., periodic and sporadic activities). This paper introduces an extension layer for the Network Interface (NI) of a network-on-a-chip in order to establish temporal and spatial partitioning over the entire chip. We describe how chip-wide segregation between different subsystems assures the absence of interference for time-triggered messages and bounded latencies for rate-constrained messages. The configuration of the NIs establishes guarding windows for time-triggered messages and traffic shaping of rate-constrained messages.

Co-simulation framework for networked multi-core chips with interleaving discrete event simulation tools

The simulation of networked multi-core chips is a significant research problem in large embedded applications. Although multi-core processors in embedded systems offer increased computational resources and performance, many applications still require distributed systems with multiple of these processors to satisfy resource requirements and provide fault-tolerance at system level. This paper introduces a framework for the co-simulation of a distributed system (i.e., off-chip networks, end-systems) with multi-core chips based on networks-on-a-chip. Simulation components are presented for the synchronization and data exchange between these simulators. A realization is performed using the simulator GEM5 for the chip level, the simulator OPNET for the cluster level and components for communication and synchronization via TCP/IP. An evaluation for a use case demonstrates the utility of the framework to analyse applications and their timing on networked multi-core chips.

Off-Chip/On-chip Gateway Architecture for Mixed-Criticality Systems Based on Networked Multi-core Chips

Multi-core processors promise improved performance and a higher physical integration by combining functions of different criticality levels in one platform. Networked multi-core chips are required to achieve a system reliability beyond the reliability of a single chip and to satisfy resource requirements exceeding the capacity of a single chip. As a consequence, hierarchical platforms emerge in which cores inside a multi-core chip interact by on-chip networks whereas multi-core chips are interconnected by off-chip networks. This paper presents gateways for establishing such a hierarchical platform. We support message-based NoCs and off-chip networks with different timing models, while also supporting real-time guarantees, fault isolation and protocol transformations. The gateways are implemented in a simulation environment based on GEM5/GARNET and experimentally evaluated.

Validation Framework for Time-Triggered System-of-Systems

System-of-Systems (SoS) with real-time communication networks are gaining more importance for many safety relevant application areas such as automotive, medical monitoring and telemedicine in health-care systems. This paper introduces a simulation framework capable of generating and simulating application scenarios of both time-triggered and rate constrained messages with their respective communication schedules with real-time requirements. The scenarios are generated where applications are introduced over time in the SoS. After that, the inputs are processed over time with an incremental scheduler that produces a trace of schedules to be simulated using OPNET. The incremental scheduling problem for the constituent systems is formulated as an Mixed-Integer Linear Programming (MILP) problem using IBM CPLEX. In addition, the simulation framework provides verification functions in terms of the evaluation of schedulability and run-time, estimation of worst-case latency for time-triggered and rate-constrained messages.