Zaher Owda

New High-Speed Multioutput Carry Look-Ahead Adders

In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multioutput domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module.

End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips

Mixed-criticality systems combine applications at different levels of criticality on the same platform. Today, mixed-criticality integration is addressed individually at different integration levels such as the operating system, the chip-level and the cluster-level. Since many mixed-criticality systems span all of these integration levels, a system perspective of mixed-criticality applications is required. The access to remote resources located on another chip needs to be relayed via gateways involving gateways between on-chip and off-chip networks (i.e., vertical integration) and gateways between different types of off-chip networks (i.e., horizontal integration). This paper introduces a system model with gateways for end-to-end channels over hierarchical, heterogeneous and mixed-criticality networks. We focus on the timing of end-to-end channels, as well as the interoperability across gateways.

Trace-based simulation framework combining message-based and shared-memory interactions in a time-triggered platform

Multi-Processor Systems-on-a-Chip (MPSoC) based on time-triggered on-chip networks facilitate fault isolation, temporal predictability and mixed-criticality integration. In mixed-criticality systems, a shared memory can be realized on top of time-triggered message passing to effectively support heterogeneous applications with different interaction paradigms. This paper presents a simulation environment of such an MPSoC combining message-based and shared-memory interactions. We present SystemC simulation building blocks for the application cores, network interfaces and the time-triggered network-on-a-chip. The behavior of the application cores is described by Transaction-Level Modeling (TLM). We generate traces from the application software or from benchmarks, which serve as input for the access to the network interfaces. The simulation framework is evaluated using a realistic case study based on SPLASH-2 and PARSEC application benchmarks. The simulation framework is essential for early validation and design space exploration of mixed-criticality systems. The high abstraction level provided by TLM and traces ensures high simulation speeds.

On-chip networks for mixed-criticality systems

We propose the integration of a network-on-chip-based MPSoC in mixed-criticality systems, i.e. systems running applications with different criticality levels in terms of completing their execution within predefined time limits. An MPSoC contains tiles that can be either CPUs or memories, and we connect them with an instance of a customizable point-to-point interconnect from STMicroelectronics called STNoC. We explore whether the on-chip network capacity is sufficient for meeting the deadlines of external high critical workloads, and at the same time for serving less critical workloads that are generated internally. To evaluate the on-chip network we vary its configuration parameters, such as the link-width, and the Quality-of-Service (QoS), in specific the number (1 or 2) and type (high or low priority) of virtual channels (VCs), and the relative priority of packets from different flows sharing the same VC.

Simulation Environment Based on SystemC and VEOS for Multi-core Processors with Virtual AUTOSAR ECUs

The extension of time-triggered message-based on-chip architectures towards an AUTOSAR MPSoC platform helps to achieve the AUTOSAR goals, in particular with respect to fault isolation and temporal predictability. Simulation environments enable early analysis and performance tests of the software for MPSoC platforms. However, there is no simulation environment that combines on-chip network communication and AUTOSAR-based software. This paper presents a simulation environment for TIme-triggered MEssage-based multi-core platforms based on AUTOSAR (TIMEA). Simulated application cores serve as virtual Electronic Control Units (ECUs), each containing an AUTOSAR operating system and a Run-Time Environment (RTE). The presented simulation environment performs a co-simulation of the AUTOSAR software, the natural environment and the time-triggered NoC. An on-chip simulation model in SystemC is combined with AUTOSAR simulation tools from dSpace. The capability of the simulation environment is evaluated using an antilock braking use case.

Predictable and reliable time triggered platform for Ambient Assisted Living

Todays Ambient Assisted Living (AAL) architectures do not support the real-time and reliability requirements of medical monitoring and closed-loop control applications. Fault-tolerant embedded system architectures, on the other hand, do not address the openness required for the dynamic integration of AAL components. This paper present an AAL architecture based on Time-Triggered Ethernet with support for openness, real-time support and reliability. The starting point is a static allocation of communication slots to end-systems. Based on this static schedule, we perform a dynamic allocation of communication resources to the components within an end-system. Each end-system can host multiple components and the communication of these components is dynamically mapped to parts of the end-systems slot. For this purpose, admission control and resource management services are introduced that ensure temporal and spatial partitioning within end-systems. The architecture is evaluated in a simulation environment based on a medical use case.

High performance and low power dynamic circuit design

Dynamic circuit design techniques can provide high speed operation at lower silicon area requirements, compared to full static CMOS designs. In this paper, we present a memoryless pipeline dynamic design technique with a pre-evaluation phase hidden inside the precharge phase. The combinational logic is implemented with dynamic circuits that offer the desirable high speed operation while the memory elements are eliminated due to an intelligent three phase clocking scheme. According to simulation results high quality designs can be achieved, in terms of performance, energy consumption and area, with respect to alternative dynamic design styles.

A Predictable Transactional Memory Architecture with Selective Conflict Resolution for Mixed-Criticality Support in MPSoCs

Transactional memories can radically simplify the programming of mixed-criticality systems by offering atomicity, consistency and isolation guarantees between subsystems of different criticality. A major objective in mixed-criticality systems is a modular safety case where each subsystem is certified to the respective safety assurance level. The prerequisite for this modular certification is the prevention of any effect of low criticality subsystems on the temporal behavior of subsystems of higher criticality. This paper introduces a transactional memory architecture based on a time-triggered network-on-a-chip with fault isolation based on a TDMA scheme. The memory architecture contains a memory gateway for selective conflict resolution when committing transactions. The memory gateway triggers a rollback of a transaction in case higher criticality subsystems would be affected. The proposed transactional memory architecture ensures that the validation and certification of high criticality subsystems does not depend on subsystems with lower criticality.

Memory-Less Pipeline Dynamic Circuit Design Technique

A desirable characteristic of VLSI circuits is high speed operation. The use of dynamic circuit design techniques can provide high speed operation at lower silicon area requirements, compared to full static CMOS designs. Another common design technique in order to achieve high operating speed is the use of pipeline schemes. However, the higher the required operating frequency, the higher the number of stages we must implement in the pipeline. In addition, a limiting factor in cases with a large number of stages, are the restrictions imposed from the required memory elements. These memory elements not only increase the silicon area of the implementation but also restrict the maximum achievable frequency due to their internal delays. In this paper, we propose a memory-less pipeline design style, where the combinational part is implemented with dynamic circuits that offer the desirable high speed operation while the memory elements are eliminated due to an intelligent clocking scheme. Thus, the proposed design technique provides the advantage of high performance operation and at the same time compares favorably to preexisting approaches with respect to silicon overhead and power requirements.

Co-simulation framework for networked multi-core chips with interleaving discrete event simulation tools

The simulation of networked multi-core chips is a significant research problem in large embedded applications. Although multi-core processors in embedded systems offer increased computational resources and performance, many applications still require distributed systems with multiple of these processors to satisfy resource requirements and provide fault-tolerance at system level. This paper introduces a framework for the co-simulation of a distributed system (i.e., off-chip networks, end-systems) with multi-core chips based on networks-on-a-chip. Simulation components are presented for the synchronization and data exchange between these simulators. A realization is performed using the simulator GEM5 for the chip level, the simulator OPNET for the cluster level and components for communication and synchronization via TCP/IP. An evaluation for a use case demonstrates the utility of the framework to analyse applications and their timing on networked multi-core chips.