Hanan A. Mahmoud

A 10-transistor low-power high-speed full adder cell

In this paper, we introduce a high-speed low-power 10-transistor 1-bit full adder cell. The critical path consists of an XOR gate; an inverter and one pass transistor. A prototype of the proposed adder cell in 0.6 /spl mu/m CMOS technology has an average delay time of 0.084 ns. It also exhibits low average power dissipation of 0.891/spl times/10/sup -4/ watt at frequency equal to one GHz. In an n-bit adder circuit, the new adder cell will give alternate polarity for the carryout in the odd and even positions. The inverters in the structure of the proposed FA cell act as drivers. Therefore, each stage will not suffer a degradation in its deriving capabilities. This saves power, area, and time. The new cell is used to build a prototype for a 32-bit ripple carry adder. This prototype has 384 transistors and it operates at 2.8 V with an average delay of 4.1 ns, and a low power dissipation of 2.6 mW at frequency equal to 250 MHz.

An efficient low-bit rate motion compensation technique based on quadtree

Summary form only given. A quadtree structured motion compensation technique effectively utilizes the motion content of a frame as oppose to a fixed size block motion compensation technique. In this paper, we propose a novel quadtree-structured region-wise motion compensation technique that divides a frame into equilateral triangle blocks using the quadtree structure. Arbitrary partition shapes are achieved by allowing 4-to-1, 3-to-1 and 2-to-1 merge/combine of sibling blocks having the same motion vector. We propose an optimal code scheme and a temporal predictive coding for the quadtree. Simulation results show that our techniques reduce the bit rate by 40% compared to other methods.

Memory accesses reduction for MIME algorithm

Power consumption of digital systems has become a critical design parameter. An important class of digital systems includes applications such as video image processing and speech recognition, which are extremely memory dominant. In such systems, a significant amount of power is consumed during memory accesses. Reducing the number of memory accesses can considerably impact the power dissipation in the rest of the design. Therefore, optimizing an application for reduced memory access can greatly effect the overall power consumption in the entire system. This paper presents an architectural enhancement multi-stage interval-based motion estimation (MIME) algorithm that not only saves power by reducing the number of memory accesses but also significantly increases the speedup.

Hardware architecture for fast Intra mode and direction prediction in real-time MPEG-2 to H.264/AVC transcoder

In this article, we propose a hardware architecture for our fast Intra mode and direction prediction algorithm to accelerate the MPEG-2 to H.264/AVC transcoding devices. In order to eliminate the redundant operations in the transcoder, our implemented algorithm uses the DCT coefficients from the MPEG-2 decoder to predict the Intra mode and reconstruction direction for the H.264/AVC encoder. In addition, the Intra prediction process in the H.264/AVC part of the transcoder has been dramatically accelerated by using our full-search elimination technique. The empirical results show 92% reduction in the transcoding time while reducing the PSNR for less than 3.5%. The proposed architecture has achieved an operating frequency of 323MHz at a power consumption of 112 mW when implemented on Virtex-5 FPGA Development Board.

An efficient successive elimination algorithm for block-matching motion estimation

Summary form only given. Low power VLSI video compression processors are in high demand for the emerging wireless video applications. Video compression processors include VLSI implementation of a motion estimation algorithm. Many motion estimation algorithms are found in the literature. Some of them are fast but cannot guarantee an optimal solution; they can be stuck in local optima. Such algorithms are fast, consumes less power when implemented in VLSI, but they can result in high levels of distortion that cannot be accepted in many applications. On the other hand the full search block matching algorithm (FSBM) is computationally intensive and a VLSI implementation of such an algorithm has high power consumption. This paper presents an exhaustive search algorithm for block matching motion estimation. The proposed algorithm reduces the computational load with successive elimination of non-candidate blocks in the search window. Our proposed algorithm assigns each pixel to a category depending on its value. The number of categories is predetermined. The algorithm consists of number of stages, the first of which has the fewer categories, eliminating those search points that are the farthest from the match. The last stage is the FSBM but with fewer search points. This computational reduction leads to low-power VLSI implementation of the algorithm. Also, it leads to faster efficient motion estimation procedure. The correctness of this algorithm and its complexity are proved.

Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder

The standard H.264/AVC Intra frame encoding process has several data dependent and computational intensive coding methodologies that limit the overall encoding speed. It causes not only a high degree of computational complexity but also an unacceptable delay especially for the real-time video applications. Based on DCT properties and spatial activity analysis, low power hardware architecture for high throughput Full-Search Free (FSF) Intra mode selection and direction prediction algorithm is proposed. The FSF Intra prediction Algorithm significantly reduces the computational complexity and the processing run-time required for the H.264/AVC Intra frame prediction process. The ASIC implementation for the proposed architecture is carried out and synthesizing results are obtained. The heavily tested 45nm ASIC design is able to achieve an operating frequency of 140 MHz while limiting the overall power consumption to 9.01 mW, which nominates our proposed FSF Intra prediction architecture for interactive real-time H.264/AVC mobile video decoders.

Efficient low-bit-rate adaptive mesh-based motion compensation technique

This paper proposes a two-stage global motion estimation method using a novel quadtree block-based motion estimation technique and an active mesh model. In the first stage, motion parameters are estimated by fitting block-based motion vectors computed using a new efficient quadtree technique, that divides a frame into equilateral triangle blocks using the quad-tree structure. Arbitrary partition shapes are achieved by allowing 4-to-1, 3-to-1 and 2-1 merge/combine of sibling blocks having the same motion vector . In the second stage, the mesh is constructed using an adaptive triangulation procedure that places more triangles over areas with high motion content, these areas are estimated during the first stage. finally the motion compensation is achieved by using a novel algorithm that is carried by both the encoder and the decoder to determine the optimal triangulation of the resultant partitions followed by affine mapping at the encoder. Computer simulation results show that the proposed method gives better performance that the conventional ones in terms of the peak signal-to-noise ration (PSNR) and the compression ratio (CR).

Low-bit-rate generalized quad-tree motion compensation algorithm and its optimal encoding schemes

Quad-tree structured motion-compensation technique effectively utilizes the motion content of a frame as opposed to fixed size block motion compensation technique. In this paper, we propose a novel quad-tree-structured region-wise motion compensation technique that divides a frame into equivalent triangle blocks using the quad-tree structure. Arbitrary partition shapes are achieved by allowing 4-to-1, 3-to-1 and 2-1 merge/combine of sibling blocks having the same motion vector. We propose an optimal code scheme and a temporal predictive coding for the quad- tree. Simulation results show that our techniques reduce the bit rate by 40% as compared to other methods.