Sumeer Goel

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders

Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X.

On the design of low-energy hybrid CMOS 1-bit full adder cells

We present several designs for 1-bit full adder cell featuring hybrid CMOS logic style. These designs are based on a novel XOR-XNOR circuit that simultaneously produces XOR and XNOR full-swing outputs and outperforms its best counterpart showing 39% improvement in PDP. The new full-adder designs are also categorized in three main categories depending upon the implementation of the logic expression for sum and carry outputs. The results show that all the proposed designs prove to be energy-efficient and outperform several standard full-adder designs. All the designs are able to operate at low voltages without significant loss in signal integrity. The improvement in terms of PDP obtained by the best full-adder cell as compared the best standard design amounts to 24%.

Noise tolerant low voltage XOR-XNOR for fast arithmetic

With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are the characteristics for deep submicron circuits. This paper proposes a low voltage noise tolerant XOR-XNOR gate with 8 transistors. The proposed gate has been implanted in an already existing (5-2) compressor cell to test its driving capability. The proposed gate is characterized and compared with those published ones for reliability and energy efficiency. The average noise threshold energy (ANTE) and the energy normalized ANTE metrics are used for quantifying the noise immunity and energy efficiency respectively. Results using 0.18m CMOS technology and HSPICE for simulation show that the proposed XOR-XNOR circuit is more noise-immune and displays better power-delay product characteristics than the compared circuit. Also, the circuit proves to be faster in operation and works at all ranges of supply voltage starting from 0.6V to 3.3V.

Adaptive search window size algorithm for fast motion estimation in H.264/AVC standard

H.264/AVC is a new recommendation for moving picture coding, in which a lot of new techniques are used for improving encoding efficiency and reducing the bit-rate. However, it involves an exhaustive motion search across multiple block sizes and multiple reference frames leading to a linear increase in processing time. Although, the encoding quality is improved, the complexity of the encoder and computational cost are increased at the same time. We reduce the computational cost by reducing the search space without significant loss in quality. Results show that there is at least 90% reduction in computation with a maximum loss of 1.4dB.

Novel design methodology for high-performance XOR-XNOR circuit design

As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are some of the characteristics for DSM circuits. A novel design methodology for the design of energy-efficient noise-tolerant XOR-XNOR circuits that can operate at low voltages is proposed. The proposed circuits are characterized and compared with previously published circuits for reliability and energy efficiency. To test their driving capability, the proposed gates are implanted in an existing 5-2 compressor design and are shown to provide superior performance. The average noise threshold energy is used for quantifying the noise immunity. Simulation results show that the proposed circuits are more noise-immune and displays better power consumption results as well as power-delay product characteristics. Also, the circuits prove to be faster and successfully work at all ranges of supply voltage starting from 0.6 V to 3.3 V.

Biocomposite cryogels as tissue-engineered biomaterials for regeneration of critical-sized cranial bone defects.

Analysis of the in vivo regeneration capability of any tissue-engineered biomaterial is necessary once it shows potential characteristics during in vitro studies. Thus, we applied polyvinyl alcohol-tetraethylorthosilicate-alginate-calcium oxide (PTAC) biocomposite cryogel on critical-sized cranial bone defects in wistar rats for examining the comparative bone regeneration of cryogel-treated and nontreated defects over a period of 4 weeks. An in-depth analysis was performed from macroscopic level till the gene level. Bone regeneration in cryogel-treated defects was clearly evident from the results, whereas the nontreated group did not show any defect healing except at few peripheral areas. At the macroscopic level, micro-computed tomography analysis revealed new bone formation. This was further confirmed at the cellular level, wherein, new bone formation was demonstrated by hematoxylin and eosin staining. Osteoblastic differentiation was further validated by immunohistological staining of runt-related transcription factor-2 (Runx-2) protein and via calcium-phosphate crystal formation after 2 weeks through scanning electron microscopy and energy dispersive X-ray spectroscopy. Finally, at the gene level, real-time PCR analysis confirmed the mRNA expression of osteoblastic markers, that is, runx-2, collagen type I (Col I), alkaline phosphatase (ALP), and osteocalcin (OCN). Therefore, the results of in vivo cranial defect model studies suggest that PTAC biocomposite cryogels can show suitable potential for human bone regeneration.

An Efficient Data Reuse Motion Estimation Engine

We present a novel motion estimation engine (MEE) architecture that efficiently reuses search area data while fully utilizing the hardware resources. A 2-D processing element (PE) core is central to the architecture. Search area data flows both horizontally as well as vertically while the current block data is stationary. A clever PE design ensures simple but highly regular dataflow through the core avoiding long interconnect delays. For a search range of [-16,+15] and block size of 16, our architecture can perform motion estimation for 60 fps of 4CIF video at 100 MHz

Multi-Path Search Algorithm for Block-Based Motion Estimation

Block-based motion estimation algorithms are widely adopted by video coding standards due to their simplicity and good distortion performance. Amongst these, pattern based search algorithms are very popular. The basic assumption made by these algorithms is that there exists a unimodal error surface within the search window. As seen in real world video sequences, this is far from reality and the algorithms often get stuck in local minimums yielding sub-optimal results. We propose a multi-path search (MPS) algorithm that utilizes more than one path to find the absolute minima. Wrong search paths are avoided early resulting in faster search. Better motion vectors are estimated increasing the video quality, consequently reducing the bitrate requirement. MPS algorithm offers flexibility and robustness with better speed and quality. Results show that a speedup of upto 34% is achieved with slight increase in PSNR as compared to its best competitor. When compared to full search, the proposed algorithm looses only 0.1%~2% in PSNR while saving 92%~95% computations.

A novel technique for noise-tolerance in dynamic circuits

Noise issues in deep submicron CMOS VLSI circuits have an importance comparable to area, delay and power consumption issues due to aggressive scaling trends in devices and interconnections. An attempt has been made to address this problem in this paper. A new technique to make dynamic CMOS circuits noise tolerant has been proposed by the authors. Simulation results for a dynamic-CMOS NAND gate and a dynamic-CMOS 1-bit full-adder circuit show that the proposed technique has an improvement in ANTE of 6.0X over conventional dynamic logic. The proposed technique, in comparison with the twin transistor technique, proves to improve ANTE by 2.8X. There is a large power dissipation incurred during the evaluation period for certain input combinations.