Hanmant P. Belgal

Bit error rate in NAND Flash memories

NAND flash memories have bit errors that are corrected by error-correction codes (ECC). We present raw error data from multi-level-cell devices from four manufacturers, identify the root-cause mechanisms, and estimate the resulting uncorrectable bit error rates (UBER). Write, retention, and read-disturb errors all contribute. Accurately estimating the UBER requires care in characterization to include all write errors, which are highly erratic, and guardbanding for variation in raw bit error rate. NAND UBER values can be much better than 10-15, but UBER is a strong function of program/erase cycling and subsequent retention time, so UBER specifications must be coupled with maximum specifications for these quantities.

A new reliability model for post-cycling charge retention of flash memories

A well-known effect in flash memories is stress-induced leakage in a small fraction of memory cells after program/erase cycling. This paper presents a comprehensive statistical reliability model with an excellent fit to data collected on several technology generations in multi-year bakes. The leakage current is exponential in voltage and has a low but nonzero activation energy. The statistical variation is Weibull. The fraction of cells affected scales as a power law in cycle count, with significant dependence on the vertical and horizontal electric fields in cycling but little on the cycling temperature. A single model equation comprehends all of these effects. The mechanism anneals or recovers at moderate temperatures in a manner sensitive to processing details, which are discussed. A new technique is introduced to deduce the number of traps involved in the trap-assisted-tunneling (percolation) paths by correlating the effect to oxide trap density using cycling-induced erase-time push-out. The results suggest that the percolation paths consist of only a small number of traps, most likely two. Contrary to predictions that this mechanism is a hard barrier to scaling of flash memory, we show that it has been possible to reduce the effect by several orders of magnitude over the course of several generations of technology scaling.