Neal Mielke

Bit error rate in NAND Flash memories

NAND flash memories have bit errors that are corrected by error-correction codes (ECC). We present raw error data from multi-level-cell devices from four manufacturers, identify the root-cause mechanisms, and estimate the resulting uncorrectable bit error rates (UBER). Write, retention, and read-disturb errors all contribute. Accurately estimating the UBER requires care in characterization to include all write errors, which are highly erratic, and guardbanding for variation in raw bit error rate. NAND UBER values can be much better than 10-15, but UBER is a strong function of program/erase cycling and subsequent retention time, so UBER specifications must be coupled with maximum specifications for these quantities.

Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling

Charge trapping over the channel can occur from program/erase cycling of Flash memory cells, increasing the cell threshold voltage and causing threshold shifts in retention tests when charges detrap. The empirical characteristics of these effects are discussed. Trapping has a square-root dependence on program/erase cycle count. Detrapping scales with the logarithm of time and is thermally accelerated with an activation energy of 1.1 to 1.2 eV. Detrapping has only a weak dependence on electric field. These mechanisms are intrinsic, yet there is a wide variation in behavior from one cell to another related to Poisson statistical variations. Common reliability characterization methods need to be re-thought in light of the characteristics of this and other mechanisms. In particular, performing extensive program/erase cycling with no delays between cycles is unrealistic for this mechanism, and alternative distributed-cycling schemes are proposed.

A new reliability model for post-cycling charge retention of flash memories

A well-known effect in flash memories is stress-induced leakage in a small fraction of memory cells after program/erase cycling. This paper presents a comprehensive statistical reliability model with an excellent fit to data collected on several technology generations in multi-year bakes. The leakage current is exponential in voltage and has a low but nonzero activation energy. The statistical variation is Weibull. The fraction of cells affected scales as a power law in cycle count, with significant dependence on the vertical and horizontal electric fields in cycling but little on the cycling temperature. A single model equation comprehends all of these effects. The mechanism anneals or recovers at moderate temperatures in a manner sensitive to processing details, which are discussed. A new technique is introduced to deduce the number of traps involved in the trap-assisted-tunneling (percolation) paths by correlating the effect to oxide trap density using cycling-induced erase-time push-out. The results suggest that the percolation paths consist of only a small number of traps, most likely two. Contrary to predictions that this mechanism is a hard barrier to scaling of flash memory, we show that it has been possible to reduce the effect by several orders of magnitude over the course of several generations of technology scaling.

Reliability performance of ETOX based flash memories

The reliability performance of a 64 K flash memory based on a single-transistor, floating-gate memory cell is considered. The reliability performance of these memories, before program/erase cycling, matches that of UV EPROMs. Cycling generally does not introduce defect-related failures common to some EEPROMs. However, it may aggravate two intrinsic instabilities found in the UV EPROM (intrinsic charge loss and the DC program disturb mechanism). Experience shows that these are related effects caused by injection of holes during the erase step of the cycle. High source-to-substrate electric fields, during erase, generate these holes. Channel hot electron injection, for programming, plays no significant role in the observed degradation. These cycling effects can be addressed through incorporation of additional margin into the flash cell. Through such cell optimization, the reliability of these memories is made equivalent to that of conventional UV EPROMs, even after hundreds of program/erase cycles. >

Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown

Gate oxide breakdown is a key mechanism limiting IC lifetime. Breakdown is typically characterized on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This work compares the predictions of capacitor-based models to results from accelerated lifetest of logic CPU products. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that an important factor was the different sensitivities of logic circuits vs. cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data including these effects. Once a model is validated, the paper discusses how it can be used to assess the reliability impact of changes in processing, use conditions, and circuit design

New EPROM Data-Loss Mechanisms

Data-loss mechanisms in present-generation EPROMs have been studied. Defect-related data loss is primarily due to interpoly-oxide defects. This is a change from the previous generation and introduces a new EPROM failure mode--column data loss. Contamination-compensation is found to be due as much to field-driven motion as to diffusion, and one result is that contaminated regions can exhibit charge gain as well as charge loss. Intrinsic charge loss is attributed to detrapping of electrons from the oxide layers rather than to loss of stored charge, suggesting that with proper screening of defects EPROM data retention is effectively unlimited.

Via delamination-a novel electromigration failure mechanism

Via delamination, a novel electromigration failure mechanism, has been investigated and understood. The mass transport model, in conjunction with environmental, thermal, and mechanical stresses was proposed to explain this failure mechanism. Process enhancements, which include lowering the thin film stresses and strengthening the adhesion between the tungsten plug/metal stack and metal/inter-level dielectric interfaces, have effectively eliminated this reliability failure mode.

The impact of PMOST bias-temperature degradation on logic circuit reliability performance

This work investigated the impact of pMOST bias-temperature (BT) degradation on logic products speed (Fmax) and minimum allowed operating voltage (Vccmin). BT degradation occurs during the product Burn-In and under the normal circuit operation. The interaction of device degradation and circuit performance is explained. Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanism and degradation models are proposed to explain the interaction of fluorine with device and circuit reliability. Process optimization, such as fluorine implant, can be used to reduce the pMOST BT impact on circuit degradation. Reliability guardband in Fmax and Vccmin is recommended, as part of the production testing to ensure reliable logic product performance and functionality during the products lifetime. A guardband methodology is also discussed in the paper.

Drain Read Disturb Assessment of NOR Flash Memory

Drain read disturb (RD) is becoming an intrinsic reliability concern for NOR flash scaling and MLC operation. A drain RD time-to-error model has been generated which takes into consideration the voltage dependence, read cycling, and Poisson random statistics. This model can be used to optimize the circuit read timing design and to assess process improvement to ensure that products meet the customer spec and lifetime usage.

Ambient Use-Condition Models for Reliability Assessment

We describe methods of computing reliability acceleration for realistic temperature/humidity use-condition models. We extract outdoor temperature/humidity models based on NOAA data, and indoor and automotive interior models by using the NOAA data combined with additional data which characterizes thermal and human behavior (thermostat settings). We compare predictions of these models with traditional reliability assessments, and provide useful models to represent the results