Kiran Pangal

Hydrogen plasma enhanced crystallization of hydrogenated amorphous silicon films

We report that a room temperature hydrogen plasma exposure in a parallel plate diode type reactive ion etcher can reduce the time required for the subsequent thermal crystallization of amorphous silicon time by a factor of five. Exposure to hydrogen plasma reduces the incubation time, while the rate of crystallization itself is not greatly affected. This plasma enhanced crystallization can be spatially controlled by masking with patterned oxide, so that both amorphous and polycrystalline areas can be realized simultaneously at desired locations on a single substrate. The enhancement of crystallization rate is probably due to the creation of seed nuclei at the surface. The films have been characterized by UV reflectance, x-ray diffraction, plan view transmission electron microscopy, Fourier transform infrared absorption, secondary ion mass spectroscopy, and four-point probe measurement of electrical conductivity.

High electron mobility polycrystalline silicon thin-film transistors on steel foil substrates

Thin-film transistors have been fabricated in polycrystalline silicon films on steel foil. The polycrystalline silicon films were formed by the crystallization of hydrogenated amorphous silicon, which had been deposited on 200-μm-thick foils of stainless steel coated with ∼0.5-μm-thick layers of SiO2. We employed crystallization temperatures (and duration) of 600 °C (6 h), 650 °C (1 h), and 700 °C (10 min). Top-gate transistors made from films crystallized at 650 °C have an average electron field-effect mobility of 64 cm2/V s, with equal values in the linear and saturated regimes. Thus steel substrates permit a substantial reduction in crystallization time over glass substrates, and afford polysilicon with high electron mobility.

Integration of amorphous and polycrystalline silicon thin-film transistors through selective crystallization of amorphous silicon

Selective exposure of a hydrogenated amorphous silicon (a-Si:H) film to a room-temperature hydrogen plasma using a patterned masking layer and a subsequent anneal at 600 °C, results in patterned polycrystalline and amorphous silicon regions. However, most of the hydrogen in the amorphous silicon is lost, leading to severe degradation in its properties. In this letter, we report the rehydrogenation of amorphous silicon films following this anneal to give a-Si:H thin-film transistors with a mobility as high as 1.2 cm2/V s and ON/OFF current ratios of ∼106. This process was used to integrate amorphous and polycrystalline silicon transistors on a single substrate with only one more lithography and processing step than that required for a single type of transistor.

p Channel thin film transistor and complementary metal-oxide-silicon inverter made of microcrystalline silicon directly deposited at 320∞C

Abstract We report a p channel thin film transistor (TFT) made of directly deposited microcrystalline silicon (μc-Si). The μc-Si channel material is grown by plasma-enhanced chemical vapor deposition (PECVD) using dc excitation of a mixture of SiH4, SiF4 and H2, in a process similar to the deposition of hydrogenated amorphous silicon (a-Si:H). The deposition temperature for the μc-Si is 320°C and the highest post-deposition TFT process temperature is 280°C. By integrating this p TFT on a single μc-Si film with an n channel TFT, we fabricated a complementary metal–oxide–silicon (CMOS) inverter of deposited μc-Si. The p channel μc-Si TFT represents a breakthrough in low-temperature Si TFT technology because p channel TFTs of a-Si:H have not been available to date. The integrated CMOS inverter is the building block of a new digital circuit technology based on directly deposited μc-Si.

Effect of Plasma Treatment on Crystallization Behavior of Amorphous Silicon Films

The crystallization of amorphous silicon (a-Si:H) deposited by plasma enhanced chemical vapor deposition (PECVD) by thermal annealing is of great interest for display and silicon-on-insulator (SOI) technologies, though long anneal times (about 20 hrs) at 600 °C are typically required. We report that a room temperature hydrogen plasma exposure in a parallel plate diode type Reactive Ion Etcher (RIE) can reduce this crystallization time by a factor of five. This plasma enhanced crystallization can be spatially controlled by masking with patterned oxide, so that both amorphous and polycrystalline areas can be realized simultaneously at desired locations. This effect is due to the creation of seed nuclei at the surface, which enhance crystallization rates.

Hydrogen plasma-enhanced crystallization of amorphous silicon for low-temperature polycrystalline silicon TFT's

It has recently been discovered that a room temperature hydrogen plasma could reduce the crystallization time at 600/spl deg/C of hydrogenated amorphous silicon films by a factor of five to a reasonable four hours. Further, the process can be spatially controlled by masking with a patterned oxide. In this abstract, we report for the first time the successful application of this method to an all low-temperature (/spl les/600/spl deg/C) TFT fabrication process. Good performance with mobility of 40-35 cm/sup 2//Vs and an ON/OFF ratio of 4/spl times/10/sup 5/ has been achieved with a crystallization time of only four hours.

Noninvasive measurement of charging in plasmas using microelectromechanical charge sensing devices

The plasma induced charging of surfaces in a plasma during semiconductor processing has been measured noninvasively using microelectromechanical devices. We have designed, modeled, and fabricated microcantilevers to act as charge sensing probes. The devices exhibit a mechanical deformation when charged, which is probed in situ by optical techniques, or measured by optical inspection after removal from plasma. Charging voltage measurements in a parallel‐plate reactive‐ion‐etching reactor show that more charging is evident at the electrode edge, and that the charging is a strong function of input rf power, chamber pressure, and flow rate of gases.

Integrated amorphous and polycrystalline silicon thin-film transistors in a single silicon layer

Using a masked hydrogen plasma treatment to spatially control the crystallization of amorphous silicon to polycrystalline silicon in desired areas, amorphous and polycrystalline silicon thin-film transistors (TFTs) with good performance have been integrated in a single film of silicon without laser processing. Both transistors are top gate and shared all process steps. The polycrystalline silicon transistors have an electron mobility in the linear regime of /spl sim/15 cm/sup 2//Vs, the amorphous silicon transistors have a linear mobility of /spl sim/0.7 cm/sup 2//Vs and both have an ON/OFF current ratios of >10/sup 5/. Rehydrogenation of amorphous silicon after the 600/spl deg/C crystallization anneal using another hydrogen plasma is the critical process step for the amorphous silicon transistor performance. The rehydrogenation power, time, and reactor history are the crucial details that are discussed in this paper.

Thin-film transistors in polycrystalline silicon by blanket and local source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625/spl deg/C or 1000/spl deg/C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600/spl deg/C, have a linear field-effect mobility of /spl sim/35 cm/sup 2//Vs and an ON/OFF current ratio of /spl sim/10/sup 6/, and TFTs with a maximum process temperature of 1000/spl deg/C, have a linear field-effect mobility of /spl sim/100 cm/sup 2//Vs and an ON/OFF current ratio of /spl sim/10/sup 7/. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600/spl deg/C showed a nearly twofold improvement in mobility (72 versus 37 cm/sup 2//Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current.

High-performance polysilicon thin film transistors on steel substrates

We fabricated thin film transistors in polycrystalline silicon on steel substrates. The polycrystalline silicon films were made by thermally annealing hydrogenated amorphous silicon precursor films, which had been deposited on stainless steel coated with0.5 lm thick 810∞C-annealed SiO2. We employed annealing temperatures ranging from 600∞C, which is the furnace annealing temperature limit for conventional glass substrates, to 750∞C. Films were crystallized at 650∞C in 1 h with 1-h hydrogen plasma seeding, at 700∞C in 10 min either with or without hydrogen plasma seeding, and at 750∞C in 2 min. The best top-gate transistors were made from films crystallized at 650∞C and had an average electron field-eAect mobility of 64 cm 2 /V s in both the linear and saturated regimes. Thus steel substrates permit a substantial reduction in crystallization time over conventional glass substrates, and produce polycrystalline silicon with an electron mobility greater than other substrates. ” 2000 Elsevier Science B.V. All rights reserved.