Hans Artmann

Porous Silicon in a Semiconductor Manufacturing Environment

In the Bosch-proprietary “advanced porous silicon membrane process”, porous silicon (PSi) is used for the first time in high-volume industrial production of microelectromechanical devices. Nanoporous silicon acts as an auxiliary layer during manufacturing of monolithically integrated pressure sensors in a mixed-signal IC process supplemented by microelectromechanical-systems-specific steps in the front end of line. In this paper, the technical design and performance of a fully automated production tool capable of high-volume fabrication of PSi under the specific constraints of a semiconductor manufacturing environment are discussed. The process requires stringent control on the PSi layer thickness, uniformity, porosity, and morphology. The impact of chamber and electrode geometry, the electrolyte flow, and the mode of current coupling into the wafer back side on the uniformity of the PSi layer is addressed. The need for a well-defined PSi morphology demands high reproducibility and stability of the electrolyte composition, particularly with respect to the hydrofluoric acid concentration.

Porous silicon technique for realization of surface micromachined silicon structures with large gaps

Abstract The characteristics of vibrating microsystems are strongly influenced by air damping. With a porous silicon (PorSi) sacrificial layer technique, the substrate gap is enhanced by a factor of >10 to obtain high Q . Test structures with substrate gaps up to 100 μm and roughness Q factor measurements with electrostatic-driven test structures demonstrating a Q factor increase of about 100% at ambient pressure are presented and discussed.

Monocrystalline Si membranes for pressure sensors fabricated by a novel surface micromachining process using porous silicon

We developed a novel surface micromachining process to fabricate monocrystalline silicon membranes covering a vacuum cavity without any additional sealing steps. Heart of the process is anodic etching of porous silicon, annealing and epitaxial growth. The porous silicon layer consists of two parts, a starting mesoporous silicon layer with low surface porosity and a nanoporous silicon layer with a high porosity. The following annealing step removes native oxide within the later cavity, and the surface is sealed for the subsequent epitaxial layer deposition. The observed stacking fault density in the epitaxial layer about 1E5 cm-2. The temperature budget of the following ASIC-process leads to a complete transformation of the nanoporous silicon layer into a large cavity. The whole structure can be used as a pressure sensor. The estimated pressure in the cavity is smaller than 1 mbar. First integrated pressure sensors have been fabricated using this process. The sensors show a good linearity over the whole pressure range of 200 mbar to 1000 mbar. This novel process has several advantages compared to already published processes. It is a “MEMS first” process, which means that after the epitaxial growth the surface of the wafer is close to a standard wafer surface. Due to full IC compatibility, standard ASIC processes are possible after the fabrication of the membrane. The use of porous silicon enables a high degree of geometrical freedom in the design of membranes compared to standard bulk micromachining (KOH, TMAH). The monocrystalline membranes can be fabricated with surface micromachining without any additional sealing or backside processing steps.