R.B. Iverson

A stochastic algorithm for high speed capacitance extraction in integrated circuits

Abstract We present the theory of a novel stochastic algorithm for high-speed capacitance extraction in complex integrated circuits. The algorithm is most closely related to a statistical procedure for solving Laplaces equation known as the floating random-walk method. Overall computational efficiency stems from various factors: suitability to rectilinear geometries, statistical-error cancellation, selective integration over Gaussian surfaces and direct capacitance-matrix evaluation. Our analysis begins with Laplaces equation for a scalable square domain, subject to arbitrary Dirichlet conditions. A boundary-integral solution is then found, from which are obtained integrals for electric potential and electric field at the domain center. An electrode-capacitance integral is next derived. This integral is expanded as an infinite sum, and probability rules that statistically evaluate the sum are deduced. These rules define the algorithm. Three sources of numerical error associated with the algorithm have been identified. They are series-truncation error, space-discretization error and statistical error. All these errors can be adequately controlled through proper adjustment of algorithm parameters.

Performance of random-walk capacitance extractors for IC interconnects: A numerical study

Abstract With ever-shrinking feature geometries, multilevel IC interconnects will greatly influence overall circuit behavior. In particular, efficient numerical evaluation of 3D IC-interconnect capacitance is essential to achieving targeted design goals. Previously, we have reported a new random-walk (RW) algorithm for extracting capacitance of complex multilevel IC interconnects [see, Y.L. Le Coz and R.B. Iverson, Solid-St. Electron. 35, 1005 (1991)]. Here, for the first time, we present a numerical study concerning the influence of interconnect complexity on RW-extractor performance. Of primary interest, are the empirical relationships among geometric complexity, run time, and memory usage. We also include, for reference, comparisons with conventional finite-element (FE) and boundary-element (BI) capacitance extractors. Despite the general computational limitations of these conventional extractors, we have attempted to normalize numerical errors to a single common value. The problem geometry selected for our study consists of a long “bus” wire situated beneath a series of shorter cross wires. Problem complexity is controlled by increasing the bus-wire length and adding cross wires. We have found that at 1% normalized error in bus-wire self-capacitance, the RW extractor has the shortest execution time, which is uniquely independent of problem complexity. In addition, because the RW extractor requires no numerical meshing, an RW:BI:FE memory-usage ratio of 1:103:107 was observed. We conclude that the RW method may possibly excel in the high-complexity regime characteristic of multilevel IC interconnects.

A floating random-walk algorithm for extracting electrical capacitance

In 1991, we developed a floating random-walk algorithm to extract electrical capacitance in 2D structures. Since then, our work has evolved into a powerful commercial 3D CAD tool, QuickCap™, capable of finding capacitance in integrated circuits (ICs) represented by multi-gigabyte databases. The algorithm has proven to be exceptionally powerful and is now finding acceptance in an application area traditionally dominated by deterministic algorithms. We present the theory underlying the floating random-walk algorithm: a formulation of capacitance as an integral of infinite dimensionality evaluated by Monte Carlo integration. A single Monte Carlo sample of the integral corresponds to a floating random-walk. We also discuss performance characteristics of QuickCap and we summarize our contributions in other application areas.

A high-speed capacitance extraction algorithm for multi-level VLSI interconnects

The authors present preliminary results of a novel stochastic algorithm for high-speed capacitance extraction in multi-level VLSI interconnects. The algorithm is related to a statistical procedure for solving Laplaces equation known as a floating random-walk method. Benchmark calculations for three-dimensional cross-wire geometries were performed on a MAC IIfx personal computer, operating at 0.3 MFLOPS. Execution times were typically 40 s for an accuracy of less that 5%. Overall computational efficiency stems from various factors: suitability to rectilinear geometries, statistical-error cancellation, selective integration over Gaussian surfaces, and direct capacitance-matrix evaluation.<<ETX>>

THEORY OF A FLOATING RANDOM-WALK ALGORITHM FOR SOLVING THE STEADY-STATE HEAT EQUATION IN COMPLEX, MATERIALLY INHOMOGENEOUS RECTILINEAR DOMAINS

Abstract We present the theory and preliminary numerical results for a new random-walk algorithm algorithm solves the steady-state heat equation subject to Dirichlet boundary conditions. Our emphasis is the analysis of geometrically complex domains made up of piecewise-rectilinear boundaries and material interfaces. This work is principally motivated by the semiconductor industry, specifically, their aggressive development of so-called multichip module (MCM) technology. We give a mathematical derivation of the surface Greens function for Laplaces equation over a square region. From it, we obtain an infinite multiple-integral series expansion yielding temperature at any space point in the actual heat-equation problem domain. A stochastic floating random-walk algorithm is then deduced from the integral series expansion. To determine the volumetric thermal distribution within the domain, we introduce a unique linear, bilinear, and trigonometric splining procedure. A numerical-verification study employing t...

A methodology for full-chip extraction of interconnect capacitance using Monte Carlo-based field solvers

We present a full-chip extraction methodology for evaluating self-capacitance of interconnects in complex digital ICs. We propose that a Monte Carlo-based field solver be used to evaluate critical net capacitances and to accurately characterize a faster, less accurate empirical extractor. The fast extractor can then be used to find noncritical net capacitances. To facilitate a priori partitioning of nets into critical and noncritical categories, we have developed a procedure for estimating absolute computational error of any capacitance extractor. We also report that Monte Carlo extractors can efficiently evaluate coupling capacitance between IC nets. In this case, statistical error cancellation occurs during a subsequent circuit simulation.

A high-speed multi-dielectric capacitance-extraction algorithm for MCM interconnects

The authors report an extension of a stochastic algorithm for capacitance extraction in complex two- and three-dimensional multidielectric structures. The algorithm has applications in the area of circuit modeling of multichip modules. The extension is in the form of a simple probability rule that depends on the ratio of electric permittivities across dielectric interfaces. Computational results are presented for a two-dimensional cross-section of a wire running over a dielectric and ground plane. Results are also presented for a three-dimensional interconnect via partially embedded in a dielectric over a ground plane. All computations were performed on a personal computer. Execution times were nominally five minutes for statistical errors ranging from one to ten percent, depending on dimensionality and value of the dielectric constant. An extraction methodology was devised for large conductor arrays based on superimposing a geometrical hashing grid.<<ETX>>

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnect-capacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-/spl kappa/ polymeric dielectrics used in high-performance ICs. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chips 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs-GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

Modeling of metal-over-silicon microstrip interconnections: the effect of SiO/sub 2/ thickness on slow-wave losses

A theoretical model for a metal-over-silicon microstrip interconnection is presented using a quasi-TEM approximation. We consider in this paper several physical effects, including: SiO/sub 2/ insulator layer, slow-wave substrate coupling, conductor resistance, skin-effect degradation, distributed RC propagation, and signal dispersion. We have examined, in particular, the influence of an underlying SiO/sub 2/ insulator layer, as previous studies have not included such a layer. Pulse propagation has been studied for durations down to 50 ps, suitable for 10 GHz clocks. We have found that pulse attenuation is reduced dramatically as the thickness of the SiO/sub 2/ layer is increased.

Development of a random-walk algorithm for IC-interconnect analysis: 2D TE benchmarks, materially homogeneous domains

Fundamentally, the electrical properties of advanced multi-level IC interconnects must be described with Maxwells equations. As an initial step towards developing an efficient methodology for electromagnetic analysis of IC interconnects, we have defined an entirely new numerical floating RW (Random-Walk) algorithm. The algorithm describes TE-mode (Transverse Electric) propagation within materially homogeneous 2D domains. The major difficulty of deriving simple, analytical surface Greens functions has been resolved by means of iterative perturbation theory. Square-domain insulator and conductor benchmark test problems yielded a mean absolute error of 0.004+0.0024i within a computed (normalized) solution range [0.0,1.0-0.3i]. Operation frequencies were 400 GHz and 1.0 GHz, for respective insulator and conductor problem sizes of 100 /spl mu/m and 10 /spl mu/m.