Hans-Jörg Pfleiderer

Symbolic pole/zero calculation using SANTAFE

The aim of symbolic analysis is to gain insight into circuit behavior. Therefore, in general, the location of the poles and zeros has to be known, which cannot be calculated symbolically for polynomials with degree greater than four. The CAD tool SANTAFE (Symbolic Analysis of Transfer Functions) applies the signal-flow graph method which tries to keep the result in a factorized form. The graphic view provided by a signal-flow graph is more visual and, as will be demonstrated, enables the user to perform circuit knowledge based approximations. A novel procedure based on symbolic Newton iteration accurately calculates high order transfer functions in the desired pole/zero form. In this way an Op-Amp was realized in a 1 ¿m 4 GHz BiCMOS process.

A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data

This paper presents the hardware realization of a recurrent scalable sorting network based on Batcher’s bitonic algorithm, which is very suitable for concurrently accessible data. Firstly, preserving the time complexity of the original bitonic sorter, the recurrent network yields a lower area complexity by reducing the communication within the network and minimizes the cost in terms of hardware resources. Secondly, an enhancement of the input registers allows the reuse of the same architecture for different input widths, where the role of each comparator level is redistributed over the network. Finally, the implementation of such a sorter has been realized in an FPGA (Field Programmable Gate Array) and shows how applications treating data block-wise can benefit from this architecture.

FPGA implementation of a flexible decoder for long LDPC codes

Over the last years LDPC codes became more and more popular because of their near Shannon limit error correcting performance. Structured code classes which ease decoder design have already been standardized for DVB-S2, IEEE WiMax 802.16e or WiFi. In this paper we introduce a flexible decoder architecture which can decode any structured or unstructured LDPC code using the identical hardware. Furthermore we present a mapping algorithm which ldquocompilesrdquo the parity-check matrix of the desired LDPC code. This concept allows adaption of the decoder controller to different LDPC codes without requiring a new synthesis run. We implemented the proposed decoder on a XILINX XC4LX160 FPGA and give bit error rates to verify design and mapping algorithm. In contrast to previously presented flexible implementations our design is able to decode LDPC codes of 30 times longer codeword lengths up toN = 65, 000.

A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier

In this paper, a reconflgurable multi-precision Radix-4 Booth multiplier structure is presented. The reconfig- urable 8 x 8 bit multiplier unit can be cascaded to form a multiplier that can adapt to variable input precision requirements. The number of bits can be extended by concatenating more stages together. For example, four 8 x8 bit units can be used to build a 16 x 16 bit Booth multiplier. In our proposed architecture, the multiplier adapts to different bit-lengths by using external control signals. The performance of our reconflgurable multiplier are compared with a parallel array multiplier and a conventional Booth multiplier. The comparison is based on synthesis results obtained by synthesizing all multiplier architectures targeting a Xilinx FPGA. The overhead resulting from our reconfiguration scheme are also evaluated and compared to a conventional Booth and array multipliers.

A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays

In this paper, a multiplexer-based concept for creating a run-time configurable array of multipliers capable of accommodating different input data word lengths is presented. In our approach, each element of a m 1× m 2 multiplier array is a parallel-parallel multiplier itself, each again comprising a number of basic arithmetic primitive cells and featuring multiplexers as controllable interconnects. Also, we distinguish between multiplier elements for unsigned and signed numbers which differ in algorithm and design. Diverse architectures are being reviewed and an estimate of hardware complexity and area consumption is given.

Large bandwidth BiCMOS operational amplifiers for SC-video-applications

Two single-ended and one fully differential high-frequency BiCMOS operational amplifiers for switched-capacitor video-applications are presented. The amplifiers feature a folded cascode structure with current sources as output loads. For the single-ended amplifiers the current mirroring is accomplished with bipolar transistors at the output of the differential pair. The common-mode feedback circuitry of the differential amplifier uses two nested differential input pairs. The amplifiers are integrated in an analog 1 /spl mu/m BiCMOS process,with an active die area of 0.72 mm/sup 2/ and 0.96 mm/sup 2/ for the single-ended and the fully differential amplifier, respectively. For all amplifiers a dc-gain of 68 dB and a unity gain frequency greater than 200 MHz was obtained.<<ETX>>

Electro-optic sampling system for the testing of high-speed integrated circuits using a free running solid-state laser

This paper deals with the indirect electro-optic sampling technique for the low-invasive detection of periodical voltage waveforms on lines in high-speed integrated circuits. The system introduced here is based on a passive mode-coupled Ti:Sapphire-Laser as light source for generating optical pulses in the subpicosecond regime. Therefore, we have to synchronize the resulting electric measurement signal and its external trigger onto the pulse repetition rate of this free running solid-state laser. The multi user function of the laser system forces us to transmit the pulses via a single-mode fiber into the measurement setup. For that purpose we developed a special optical arrangement to minimize the widening of the pulses in the time domain. The systems high-temporal resolution of nearly 10 ps in combination with its high-voltage sensitivity of about 800 /spl mu/V//spl radic/(Hz) is demonstrated by measurements of an integrated microwave frequency divider.

Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA

As hardware synthesis tries to go behavioral, system designers tend to neglect low level optimizations, e.g., retiming or resources reuse. However, complex architectures such as highly parallel sorter cores cannot be directly packed into standard devices by the electronic design automation (EDA) tools and often needs fundamental rethinking. Therefore this paper resumes a cost study of the hardware realization of a recurrent parameterizable N-sorter based on Batchers bitonic algorithm and shows how to recombine different network sizes by preserving data throughput. With the time complexity of the original bitonic sorter, the recurrent architecture yields a lower area complexity by reducing the communication within the network and minimizes the cost in terms of hardware resources. Furthermore, the validity domain of internal architectural parameter combinations demonstrate the existence of an optimal area-throughput trade-off for very large scale integration (VLSI) models based on field programmable gate array (FPGA) synthesis, as well as a full scalability of the highly parallel sorting scheme

A scalable compact architecture for the computation of integer binary logarithms through linear approximation

This paper presents the realization of a scalable architecture, the Negative Logarithmic Function (NLF), for the integer calculation of nonlinear functions. It shows how to implement the desired analog logarithm and its reciprocal function with very little logic and a maximizable accuracy. After introducing the NLF module and its properties, we describe the way the continuous function is approached in order to come across the hardware realization. A simple solution is given to reduce the error made by the approximation, as well as the architecture for the reverse transformation. To illustrate the method, examples are given in which the width of the input value has been arbitrarily fixed to 8 bits, whereas the scalable architecture supports every kind of bus width.

Modelling the glucose metabolism with backpropagation through time trained Elman nets

Type-I diabetes mellitus patients can not produce the hormone insulin endogenously. As this hormone is necessary to control the blood sugar level, which is raised by eating, insulin must be delivered exogeneously. Delivering insulin exogeneously demands correct dosage to avoid an extremely high or low blood glucose level. Most patients are not able to administer the adequate insulin dose because they are not able to predict the evolution of their own glucose level after a meal. Therefore, a model of the glucose metabolism is of crucial interest to help patients to determine correct insulin doses. These models shall be capable of predicting the course of the blood glucose level for a couple of hours with reasonable precision. In this paper a computer aided assistance system for diabetes patients running on a mobile handheld device is presented. This assistance system mainly consists of a model of the glucose metabolism, implemented by a modified Elman net. The training is performed through the BPTT algorithm where the training data were generated with an analytical non-linear glucose metabolism model that is quite realistic but cannot be adapted to every single patient. The glucose metabolism process is defined by two inputs, injected insulin and ingested glucose, and one output, namely the blood glucose. Due to the fact that metabolic processes in general have large time constants this process is characterized by the fact that the current net output, that is the blood glucose level, heavily depends on data that are not present in the current input layer any more. The Elman nets context-layer is capable of storing this information. Simulation results demonstrate that the output of this type of neural network closely follows the reference.