Christophe Layer

Using quadrature modulation for precise fault location over wired communication channels

Wire diagnosis has always been a challenge in many fields including transportation and communicating systems, yet becoming also the key for integrity, safety and security. For time-causality reasons, and for the sake of hardware complexity, it has long been assumed that measuring only the real part of signals within a diagnosis system should be enough for fault detection. However, in certain circumstances, electrical singularities remains undetected. This paper recalls that there is more to discover in the imaginary part of the reflected signal than just an argument to estimate the phase delay. The presented method provides several advantages over state-of-the-art techniques and is particularly well suited for implementations in distributed sensor networks. Accordingly, our measurements were performed through the use of an FPGA-based embedded platform with external frequency-modulation circuits and our estimations were proven quite accurate and realistic for multi-carrier signals, allowing the detection of previously undiscovered defects.

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories

The most widely used embedded memory technology, static random access memory (SRAM), is heading toward scaling problems in advanced technology nodes due to the leakage currents caused by the quantum tunneling effect. As an alternative, spin-transfer torque magnetic RAM (STT-MRAM) technology shows comparable performance in terms of speed and power consumption and much better performance in terms of density and leakage. Moreover, MRAM brings up new paradigms in system design thanks to its inherent nonvolatility, which allows the definition of new instant-on/off policies and leakage current optimization. Based on our compact model, we have developed a fully characterized system-on-chip from the basic cell up to the system architecture in a 40nm LP hybrid CMOS/magnetic process. Through simulations, first we demonstrate that STT-MRAM is a candidate for the memory part of embedded systems, and second we implement a check-pointing methodology based on the regular interrupt routines of a processor to enable a fast power on and off functionality. Using a synthetic benchmark developed in high-level programming languages intended to be representative of integer system performance, our method shows that having MRAM instead of SRAM in an embedded design brings up important energy savings. The influence of the check-pointing routine on power consumption is finally evaluated with regard to various shutdown and restart behaviors.

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

Energy efficient computing has become the key to enable the portability of new applications onto mobile devices which need to be always smaller and more powerful. As the technology node shrinks, the leakage current increases exponentially in deep submicron CMOS, so that new strategies are required in integrated systems to save power without limiting processing performances. One of the solutions is to rely on NonVolatile Memories (NVM) and their integration within complex computing systems, but the association of heterogeneous technologies remains a real challenge. In this paper, we describe a fully embedded System-on-Chip (SoC), i.e., without external memory interface. We discuss the benefits of embedding NVM elements into the system in terms of power consumption and functionality enhancements compared to an equivalent system relying on standard volatile memory blocks. We depict the complete design from the block-diagram down to the layout of the fully functional non-volatile SoC. Our methodology includes the conception of a single bit memory cell up to the benchmarking of the architecture, in a hybrid magnetic/CMOS low-power technology, regarding the industrial constraints past experimentation in the aim to reach the quality of commercial products. We present precise pre-silicon performance estimations, using different configurations of compression algorithms as reference benchmarks that show where energy is mainly consumed.

Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC

This paper describes the design and the evaluation of a low-power System-on-Chip (SoC) in an advanced hybrid 40nm magnetic/CMOS technology node. Without external memory interface, the processor of the SoC benefits from a privileged access to the embedded NVM (Non-Volatile Memory), providing means for internal data storage and integrity thanks to its inherent non-volatility. Furthermore, a method based on an IRQ (Interrupt Request) controls the instant-on/off features of the SoC at assembler level through the use of NVM elements and improves the whole system in terms of power consumption and functionality enhancements, compared to an equivalent system relying on standard volatile memory blocks only. We discuss our simulation results on the basis of still image compression benchmarks at various data throughputs and show the benefits of NVM even for rather computation intensive algorithms.

Automated phase offset correction using reflectometry in fault detection systems

Well established cable network diagnosis systems rely on reflectometry and transferometry principles to detect faults using specific signals within a frequency spectrum of a few hundreds MHz only. Huge performance improvements in terms of precision and sensitivity can be achieved with higher frequencies and signal modulation, hence revealing phase and amplitude response of the potential impedance discontinuities on the tested channel to better classify the defects. However, as for telecommunications, frequency translation requires a special care in signal processing and integrity, the relative complexity of which has discouraged its implementation in wire diagnosis systems for now. Crossing the domains with an ingenious phase-offset correction mechanism, we show that defects can be accurately detected and correctly analyzed with our system relying on quadrature modulation. The presented method provides several advantages over state-of-the-art techniques and is particularly well suited for implementations in distributed sensor networks. Accordingly, our measurements were performed using an FPGA-based embedded platform and discrete high-frequency components.

Magnetic memories: From DRAM replacement to ultra low power logic chips

The recent advent of spin transfer torque (STT) has shed a new light on MRAM with the promises of much improved performances and greater scalability to very advanced technology nodes. As a result, MRAM is now viewed as a credible solution for stand-alone and embedded applications where the combination of non-volatility, speed and endurance is key. Whereas the technology is nearing maturity for DRAM replacement, with the exception of process scaling to sub-20nm which remains a challenge, circuit designers are now actively looking at SoCs where MRAM could bring in better performance and lower power consumption in data intensive applications as well as instant-on capability in mobile applications. In this paper we present a review of the MRAM technology and a methodology for ASIC design using a custom full digital hybrid CMOS/Magnetic Process Design Kit. We finish by a few examples showing that magnetic memories can be efficiently integrated in logic designs, for both safety and low power purposes.

Nonvolatile runtime-reconfigurable FPGA secured through MRAM-based periodic refresh

A need expressed in the industry in terms of FPGA (Field Programmable Gate Array) is the radiation hardness. This paper presents a new FPGA architecture designed to meet this requirement, using a hybrid CMOS/Magnetic process that offers specific features such as non-volatility and intrinsic radiation hardness, commonly named MRAM process for Magnetic Random Access Memory process. The main idea is to use DRAM memory (Dynamic Random Access Memory) for the configuration and to use MRAM that stores the configuration to refresh the DRAM. This technique, known as scrubbing technique, enables reloading the configuration of the FPGA periodically avoiding the accumulation of errors. Therefore, the FPGA is intrinsically hardened to radiation with a low area overhead. Moreover, the power consumption is reduced and a dynamic reconfiguration is easily possible by programming the MRAM devices. Results extracted from the 2-input LUT (Look-Up Table) silicon demonstrator that has been designed, fabricated and tested are really encouraging.