Hao-Jan Chao

Logic BIST Architecture for System-Level Test and Diagnosis

This paper describes the logic built-in self-test (BIST) architecture for test and diagnosis of ASIC devices at the system level. The proposed architecture supports the at speed staggered launch-on-capture clocking scheme and includes novel features to further increase the device’s defect coverage, place-and-route ability, ease of debug and diagnosis, and reduce test power consumption. These features include equivalent clock merging for routing considerations, programmable shift modes for overheat considerations, configurable capture modes for yield loss and IR-drop considerations, as well as BIST signature diagnosis, masked-chain diagnosis, and one-chain diagnosis at the system level. Experimental results have successfully demonstrated the feasibility of using the proposed features for system-level test and diagnosis.

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

This paper describes a core-based test and diagnosis integration and automation system, called Turbo1500, which automatically synthesizes test and diagnosis logic in accordance with the IEEE 1500 standard. Turbo1500 serves two major purposes. One is for use as a core test automation tool in a system-on-chip (SOC) environment to automatically connect multiple cores from various sources and create testbenches each targeting an individual core under the control of a chip-level test access port (TAP) controller. The other is for hierarchical (block-by-block) core test and diagnosis when chips on a printed-circuit board are embedded with 1149.1 boundary scan I/O cells and cores under test and diagnosis are surrounded with 1500-compliant wrapper cells. Application experience showed that the simplicity of the IEEE 1500 standard combined with an easy-to-use automation tool can make core-based design for test and diagnosis no longer a nightmare, especially when some cores are extremely large or complex.

At-Speed Logic BIST for IP Cores

This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.

A circular pipeline processing based deterministic parallel test pattern generator

Parallel programming is an attractive solution to accelerate test pattern generation (TPG); however, the associated non-determinism often leads to non-reproducible test pattern sets. In this paper, the circular pipeline processing (CPP) principle is proposed to facilitate deterministic parallel TPG. CPP preserves the task processing orders that are necessary to ensure TPG determinism with low inter-thread synchronization overhead. Based on CPP, a deterministic parallel test pattern generator is developed; it guarantees to produce the same test pattern set regardless of the thread timing and the thread count. Experimental results on benchmark circuits show that the proposed test pattern generator exhibits close-to-linear speedup for at least up to 12 threads.

Turbo1500: Core-Based Design for Test and Diagnosis

Tool support is crucial in widespread adoption of a standard. This article describes a set of tools and associated flow for DFT insertion and test generation based on IEEE Std 1500.

Physical-design-friendly hierarchical logic built-in self-test—A case study

This paper describes an application of a physical-design-friendly hierarchical logic built-in self-test (BIST) architecture and validation methodology on a networking system-on-chip (SOC) design. The design consists of two embedded cores, each containing approximately 45 million primitives and 2.5 million flip-flops. The implemented architecture supports an at-speed staggered launch-on-capture clocking scheme and includes novel features to reduce turnaround time during engineering change order (ECO) and the devices BIST runtime. It also embeds test and diagnosis features to facilitate debugging of the device at the system level. The BIST hierarchy includes wrappers surrounding each core with access from chip-top allowing for both parallel and serial validations of the cores. This case study successfully demonstrates the feasibility of using the implemented features for speedy ECO, synergy with physical design flow, and ease of test and diagnosis.