Hao San

SAR ADC algorithm with redundancy

This paper describes a redundant algorithm for a highly reliable Successive Approximation Register (SAR) ADC where mistakes of comparator decision can be digitally-corrected. We generalize a conventional non-binary search algorithm which requires more conversion steps in the SAR ADC than the binary search algorithm, and clarify which decision errors can be digitally-corrected with the derived redundant algorithm. We also shows that the sampling speed of the SAR ADC using the proposed algorithm can be faster when the incomplete settling effects of the DAC inside the SAR ADC are taken into account.

High-resolution DPWM generator for digitally controlled DC-DC converters

This paper describes a new architecture for high-resolution digital PWM (DPWM) generator used in digitally-controlled DC-DC converters, PWM time resolution is determined by the difference between two (or more) gate delays, while that of conventional DPWM circuits is determined by gate delay itself. The proposed DPWM circuit can achieve fine time resolution with small circuits, and has low power consumption. We have also developed a systematic design method for this DPWM circuit based on the extended Euclidean algorithm. A design example that achieves 10 ps time resolution for 80 ns cycle time (i.e. 13-bit resolution) is shown to demonstrate the effectiveness of the proposed DPWM architecture.

A high-speed CMOS track/hold circuit

This paper describes the design of a high-speed CMOS track/hold circuit in front of an ADC. The track/hold circuit employs differential open-loop architecture, very linear source follower input buffers, NMOS sampling switches and bootstrap sampling-switch driver circuits for high-speed operation with 3.3 V supply voltage. SPICE simulations with MOSIS 0.35 /spl mu/m CMOS BSIM 3v3 parameters showed that it achieves the signal-to-(noise+distortion)-ratio (SNDR) of more than 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mW power consumption. A test circuit was fabricated with MOSIS 0.8 /spl mu/m CMOS process and its measured results show that the proposed circuit topology performs a track/hold operation.

Non-binary SAR ADC with digital error correction for low power applications

This paper describes techniques for creating a low-power SAR ADC with an error-correcting non-binary successive approximation algorithm; it is suitable for low power applications, performs digital error correction, and does not require analog calibration. Two techniques have been proposed for implementing low-power SAR ADCs: use of two comparators, and a charge-sharing architecture. However these techniques would normally require analog calibration of comparator offsets. Here we propose a non-binary SA algorithm that compensates for comparator offset effects in the digital domain, and so eliminates the need for analog calibration. Results of our Matlab simulation validate the effectiveness of this approach.

An element rotation algorithm for multi-bit DAC nonlinearities in complex bandpass /spl Delta//spl Sigma/AD modulators

This paper presents a technique for improving the resolution of complex bandpass /spl Delta//spl Sigma/ADCs which are used for wireless communication systems. Oversampling and noise-shaping are used to achieve high accuracy of a /spl Delta//spl Sigma/AD modulator. However when a multi-bit DAC is used inside a modulator, nonlinearities of the DAC are not noise-shaped and the SNR of the /spl Delta//spl Sigma/ADC degrades. For the conversion of complex intermediate frequency (IF) input signals, a complex bandpass /spl Delta//spl Sigma/AD modulator can provide superior performance to a pair of real bandpass /spl Delta//spl Sigma/AD modulators of the same order. This paper proposes a new noise-shaping algorithm-implemented by adding simple digital circuitry-to reduce the effects of nonlinearities in multi-bit DACs of complex bandpass /spl Delta//spl Sigma/AD modulators. We have performed simulation with MATLAB to verify the effectiveness of the algorithm, and the results show that the proposed algorithm can improve the SNR of a complex bandpass /spl Delta//spl Sigma/ADC with nonlinear internal multi-bit DACs.

An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components.

A 12-bit algorithmic (cyclic) ADC is designed and fabricated in 90nm CMOS, and only occupies as small active area as 0.037mm2. With the proposed radix-value self-estimation scheme for a non-binary 1-bit/step architecture, the accuracy requirement on analog components is largely relaxed. Therefore, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density MOM capacitors can be used to achieve small area. Furthermore, the novel radix-value self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves 62.3dB SNDR at 1.4V power supply and 1.25Msps (20MHz clocking) using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz input.

Novel Architecture of Feedforward Second-Order Multibit ΔΣAD Modulator

This paper proposes novel feedforward architecture of the second-order multibit ΔΣAD modulator with single DAC-feedback topology. The ΔΣAD modulator realizes high resolution by oversampling and noise shaping techniques. However, its SNDR (Signal to Noise and Distortion Ratio) is limited by the dynamic range of the input signal and non-idealities of circuit building blocks, particularly by the harmonic distortion in amplifier circuits. A full feedforward ΔΣAD modulator structure has the signal transfer function of unity under ideal circumstances, which means that the signal swings through the loop filter become smaller compared with a feedbacked ΔΣAD modulator. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced in the feedforward structure because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirements for amplifiers with low supply voltage. However, in conventional feedforward ΔΣAD modulator, an analog adder is needed before quantizer, and especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to extra chip area and power dissipation. In this paper, we propose a novel architecture of a feedforward ΔΣAD modulator which realizes the summation of feedforward signals without additional amplifier. The proposed architecture is functionally equivalent to the conventional one but with smaller chip area and lower power dissipation. We conducted MATLAB and SPICE simulations to validate the proposed architecture and modulator circuits.

High-Speed CMOS Track/Hold Circuit Design

This paper describes the design of a high-speed CMOSTrack/Hold circuit in front of an ADC. The Track/Hold circuit employsdifferential open-loop architecture, very linear source follower inputbuffers, NMOS sampling switches and bootstrap sampling-switch drivercircuits for high-speed operation with 3.3 V supply voltage. SPICEsimulations with MOSIS 0.35 μm CMOS BSIM3v3 parameters showed thatit achieves a signal-to-(noise+distortion)-ratio (SNDR) of morethan 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mWpower consumption.

ΔΣAD modulator for low power application

This paper proposes a new architecture of the feedforward multibit DeltaSigmaAD modulator for low power application. The SQNDR (Signal to Quantization Noise and Distortion Ratio) of DeltaSigmaAD modulator is limited by the dynamic range of the input signal and non-idealities of circuit building blocks, particularly by the harmonic distortion in amplifier circuits. In a full feedforward DeltaSigmaAD modulator structure, the signal swings through the loop filter is smaller than a feedback DeltaSigmaAD modulator. Therefore, the harmonic distortion generated inside the loop filter of the feedforward structure can be significantly reduced because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. However, in conventional feedforward DeltaSigmaAD modulator, an analog adder is needed before the quantizer, and especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to extra chip area and power dissipation. In this paper, firstly, we propose a new architecture of a feedforward DeltaSigmaAD modulator which realizes the summation of feedforward signals without additional amplifier. The proposed architecture is functionally equivalent to the conventional one but with smaller chip area and lower power dissipation. Furthermore, we extend the architecture with noise-shaping enhancement, the modulator contains a second-order loop filter can deliver a third-order noise-shaping. We conducted MATLAB simulations to validate the proposed architecture.

Second-order ΔΣAD modulator with novel feedforward architecture

This paper proposes novel feedforward architecture of a second-order DeltaSigmaAD modulator with single DAC- feedback topology. DeltaSigmaAD modulator realizes high resolution by oversampling and noise shaping technique. However, its SNDR (signal to noise and distortion ratio) is limited by the dynamic range of the input signal and non-idealities of building blocks, particularly by the harmonic distortion in amplifier circuits. Compared with a feed backed DeltaSigmaAD modulator, in a full feedforward DeltaSigmaAD modulator structure, the signal transfer function is unity under ideal circumstances. It means that the signal swings through the loop filter become smaller. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirement for amplifiers in low-voltage design. However, in conventional feedforward DeltaSigmaAD modulator, an analog adder is needed before quantizer. Especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to large chip area and extra power dissipation. In this paper, we propose a novel architecture of a feedforward DeltaSigmaAD modulator. It realizes the summation of feedforward signals without additional amplifier that is equivalent to the conventional one but smaller chip area and low-power dissipation. We also conducted MATLAB and SPICE simulations to verify the proposed architecture and modulator circuits.