Masao Hotta

Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits

This paper describes measurement of substrate noise waveforms in mixed-signal integrated circuits. This method uses wide-band chopper-type single-ended voltage comparators as on-chip noise detectors. By analyzing equivalently sampled comparator outputs in synchronized operation, the noise voltage in the auto-zero and compare modes can be measured separately, and noise waveforms were experimentally reconstructed to within 0.5-ns accuracy. The noise transmission path was analyzed, and this showed that the noise sampled at the auto-zero mode of the comparator can be used to reconstruct substrate noise waveforms with high resolution. The results also explain the influence of noise coupling on analog circuits widely used in on-chip analog-to-digital converters.

Measurement of digital noise in mixed-signal integrated circuits

This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal ICs. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits. >

Maximum-likelihood estimation of current-dipole parameters for data obtained using multichannel magnetometer

A method of reducing the influence of external noise magnetic field on the accuracy of estimating current dipole parameters is proposed. It utilizes the spatial correlation of external noises, and is applied to data measured using a multichannel magnetometer. Computer simulation demonstrates the effectiveness of the proposed method.<<ETX>>

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

A 10-bit 20-MHz A/D converter for high-quality video systems such as high-definition television, video tape recorders for business use, and digital video cameras is described. This LSI circuit uses a standard two-step parallel architecture, includes automatic gain adjustment and digital two-bit error correction, and has a sample-and-hold circuit on the chip. It is fabricated by a 4.5-GHz f/sub T/. 3- mu m-rule standard bipolar technology. Its die size is 25 mm/sup 2/, and its power consumption is 900 mW, which is about half of the lowest values reported to date. The converter can digitize video signals of up to 8.5 MHz at a conversion frequency of 20 MHz. The error in differential gain is 0.5 percent, and the error in differential phase is 0.5 degrees . >

SAR ADC algorithm with redundancy

This paper describes a redundant algorithm for a highly reliable Successive Approximation Register (SAR) ADC where mistakes of comparator decision can be digitally-corrected. We generalize a conventional non-binary search algorithm which requires more conversion steps in the SAR ADC than the binary search algorithm, and clarify which decision errors can be digitally-corrected with the derived redundant algorithm. We also shows that the sampling speed of the SAR ADC using the proposed algorithm can be faster when the incomplete settling effects of the DAC inside the SAR ADC are taken into account.

A 150-mW, 8-bit video-frequency A/D converter

The authors describe an 8-bit, extremely low-power, flash A/D converter LSI for video-frequency image signal processing. This converter uses a shallow-groove-isolated bipolar VLSI technology. It consumes only 150 mW, which is half the amount of the lowest power consumption so far reported. This low level of power consumption is achieved by the use of a comparator circuit, which is newly designed. This converter can digitize video signals of up to 10 MHz at a conversion rate of 30 MHz. A differential gain (DG) error of 1% and a differential phase (DP) error of less than 0.5/spl deg/ were observed.

A 95 mW, 10 b 15 MHz low-power CMOS ADC using analog double-sampled pipelining scheme

A very-low-power, 95 mW, 10 b 15 MHz CMOS pipelined fully differential A/D converter (ADC) is fabricated using analog double sampling. Excellent power reduction is achieved using this sampling technique and a 3.3 V supply voltage design for comparator circuits. The 5 V internal supply is generated by an on-chip 3.3 V to 5 V charge pumping voltage generator. The fully differential approach is compatible with this type of implementation. The amplifier has a triple cascode configuration to achieve a gain of 80 dB. The converter exhibits good performance at 15 MHz, very good input bandwidth of 7.53 MHz at the 15 MHz conversion rate, and good linearity. Excellent power dissipation is observed.<<ETX>>

An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate

An 8-b flash analog-digital (A/D) converter (ADC) LSI for high-speed data acquisition systems such as digital oscilloscopes and wave digitizers is described. This converter can convert analog input signals over the Nyquist frequency (up to 200 MHz) at a conversion rate of 300 megasamples per second (Ms/s) without glitch errors. In addition, it can be operated at up to 440 Ms/s when input frequency is as low as 100 kHz. This ADC is fabricated by a 2.5- mu m, 10-GHz f/sub T/, Si bipolar technology called the advanced sidewall base contact structure (advanced SICOS) technology. For high-performance glitch error suppression, an inhibitory circuit and a comparator design with an inner clock buffer are developed. Both techniques require few hardware additions. >

A 3.6 V 4 W 0.2cc Si power-MOS-amplifier module for GSM handset phones

Reliable cost-effective and small power amplifiers with high output power and efficiency are required for cellular handset phones. Present Si-MOS power-amplifier modules are inherently superior in terms of thermal stability and single-voltage operation, and yet their performance and size are comparable to or even better than those of GaAs-FET power-amplifier modules. These modules are used by the majority of GSM-cellular handset-phone manufacturers worldwide. Since Li-ion batteries with high-energy densities have been widely used in cellular handset phones, 3.6 V supply operation (3.6 V system) is required for next-generation amplifier modules. However, a 3.6 V 4 W RF power-amplifier module has not yet been developed, even by using GaAs devices.

A 85-mW, 10-bit 40-Ms/s ADC with decimated parallel architecture

The design of a low-power, 10-bit 40-Ms/s ADC integrated in 0.8-/spl mu/m multi-threshold CMOS is presented. This fully differential design employs a decimated parallel combination of single-bit and multi-bit per stage pipelined architectures to achieve this performance. The ADC, targeted for high resolution video terminals, dissipates 85-mW from 2.7-V supply, and occupies an area of 1.9 by 2.1-mm/sup 2/.<<ETX>>