Tatsuji Matsuura

A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver

This paper presents a fully integrated SAR ADC for GSM/WCDMA/LTE triple-mode transceiver (RFIC) with non-binary DAC structure and digital correction techniques. All blocks including input buffer, ADC core, bias, references and ADC logics are implemented in a single chip with a small die area of 0.044 mm /0.066 mm for ADC core and ADC logic. The proposed ADC does not require off-chip decoupling capacitor for reference voltage by employing charge-sharing topology. Reconfigurable structure is used for multi-mode operation by adjusting ADC speed and noise, where SNDR of 67.0 dB in GSM and 58.2 dB in WCDMA/LTE are achieved at the sampling frequencies of 52 MS/s and 80 MS/s, respectively.

Non-binary cyclic and binary SAR hybrid ADC

We propose a hybrid A/D converter consist of non-binary or beta-weighted cyclic ADC, and binary SAR ADC. The upper bits or MSBs are converted by beta-weighted cyclic ADC. With the help of automatic beta-value estimation, MSBs are converted accurately. One of the capacitors of the cyclic ADC is composed by a binary weighted capacitor array. After MSB conversion, residual voltage of cyclic ADC remains on the capacitor array. Lower bits or LSBs are determined using this capacitor array by Successive Approximation (SAR-) algorithm. Beta-weighted cyclic brings high accuracy to the ADC, and lower bit SAR-ADC helps to improve conversion speed and to reduce power consumption.

Integrated CMOS ADC — Tutorial review on recent hybrid SAR-ADCs

Recently, SAR-ADC architecture is often used as an integrated ADC architecture in VLSI chip. The advantage of SAR ADC is the non-necessity of high-gain OP amps, low power consumption features, and its suitability to fine process. On the other hand, disadvantage with simple SAR architecture, however, is its difficulty to achieve high-sampling frequency and/or high SNDR. There are many proposals on SAR ADC operation speed improvement. Apart from time-interleaving, pipelined SAR approach helps to speed up the A/D conversion. Also, many precision improvement methods are proposed. Among these, hybrid architecture such as combination of SAR and oversampling or noise-shaping is useful to improve SNDR of the ADCs. This tutorial reviews recent progress on CMOS hybrid ADC architectures with high speed and/or high SNDR hybrid ADCs.

A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components

This paper presents a prototype of 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redantancy of non-binary ADC tolerates the non-idealities such as capacitor mismatch and finite amplifier gain, the design consideration of this high accuracy ADC are be focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier. The proposed proof-of-concept cyclic ADC is designed and fabricated in TSMC 90nm CMOS technology. Peak SNDR×81.9dB is achieved while Fs×80kSPS with a poor gain of the amplifier as low as 66dB dissipating 8mW at VDD×3.3V in analog circuits.

Non-binary cyclic ADC with correlated level shifting technique

A proof-of-concept non-binary cyclic ADC with proposed correlated level shifting (CLS) technique is designed and fabricated in 90nm CMOS technology. By applying the odd/even structure to a multiplying digital-to-analog converter (MDAC), the amplifier with CLS can be used for a cyclic ADC, so that the allowable dynamic range of the proposed cyclic ADC almost is doubled comparing to the conventional cyclic ADC. As a result, the SNDR of ADC can be improved with smaller power penalty. Measurement results of the prototype confirm the effectiveness of the proposed CLS technique for cyclic ADC.

A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion

This paper presents a 10-bit, 10Ms/s pipeline cyclic analog-to-digital converter (ADC) in 90nm CMOS technology. The proposed ADC is designed and fabricated in 3-stage pipeline structure, and each pipeline stage is a non-binary cyclic ADC based on β-expansion. The output bit-number of stages is selected as 4-4-8 bits according to the considerations of chip area, conversion speed and total power consumption. We also optimized the capacitor value and amplifier parameter of the MDAC at each stage to satisfy the required performance of ADC. The radix value of non-binary output code can be estimated with our proposed algorithm, and the 16-bit output non-binary-codes are converted to 10-bit binary-codes by off-chip processing. The redundancy of non-binary ADC tolerates the non-linearity errors of conversion so that required accuracy of analog components is dramatically relaxed. The prototype ADC achieves a measured SNDR of 61.07dB at 10Ms/s even with an amplifier with poor DC gain as low as 45dB. The measured DNL is +0.32/-0.61LSB and INL is +0.79/-0.67LSB at 311.3kHz input. The total power consumption of ADC is 4.7mW at 1.2V supply and it occupies an active area of 0.068mm2.