Haralampos-G. D. Stratigopoulos

Evaluation of Analog/RF Test Measurements at the Design Stage

We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides a general framework to compare alternative test solutions that are continuously being proposed toward reducing the high cost of specification-based tests. The key idea of the method is to build a statistical model of the circuit under test and the test measurements using nonparametric density estimation. Thereafter, the statistical model can be simulated very fast to generate an arbitrarily large volume of new data. The method is demonstrated for a previously proposed built-in self-test measurement for low-noise amplifiers. The result indicates that the new synthetic data have the exact same structure of data generated by a computationally intensive brute-force Monte Carlo circuit simulation.

Diagnosis of Local Spot Defects in Analog Circuits

We present a method for diagnosing local spot defects in analog circuits. The method aims to identify a subset of defects that are likely to have occurred and suggests to give them priority in a classical failure analysis. For this purpose, the method relies on a combination of multiclass classifiers that are trained using data from fault simulation. The method is demonstrated on an industrial large-scale case study. The device under consideration is a controller area network transceiver used in automobile systems. This device demands high-quality control due to the reliability requirements of the application wherein it is deployed. The diagnosis problem is discussed by taking into consideration the realities of this case study.

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to directly measure datasheet specifications. To reduce the involved costs it is required to eliminate specification tests or use instead lower-cost alternative tests. However, this is too risky if the resultant fault coverage and yield coverage metrics of the new test approach are not estimated accurately. This paper proposes a methodology to efficiently derive a set of most probable failing and marginally functional circuit instances. Based on this set, we can readily define and estimate fault coverage and yield coverage metrics. Our methodology reduces the required number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the methodology is applied to a radio frequency low-noise amplifier.

Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device. It can be used to refine the process/design in time so as to guarantee high production yield. In the case of migration of production of a specific device from a source fab to a target fab, yield estimation in the target fab can be accelerated by employing information from the source fab, assuming that the process parameter distributions in the two fabs are similar, but not necessarily the same. In this paper, we employ the Bayesian Model Fusion (BMF) technique for efficient yield prediction of a device in the target fab. BMF adopts prior knowledge from the source fab and combines it intelligently with information from a limited number of early silicon wafers from the target fab. Thus, BMF allows us to obtain quick and accurate yield estimates at the onset of production in the target fab. The proposed methodology is demonstrated on an industrial RF transceiver.

Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times

The high cost of mixed-signal circuit testing has sparked a lot of interest for developing alternative low-cost techniques. Although it is rather straightforward to evaluate an alternative test technique in terms of test cost reduction, proving the equivalence between an alternative and the standard test technique in terms of test metrics, before actually deploying the alternative test technique in production, is very challenging. The underlying reason is the prohibitive simulation effort that is required. Existing test metrics evaluation methodologies are efficient only for circuits that can be simulated fast at transistor-level. In this paper, we propose a test metrics evaluation methodology for circuits with long simulation times that is based on a combination of behavioral modeling and statistical blockade. The methodology is demonstrated on a built-in self-test strategy for ΣΔ analog-to-digital converters.

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.

One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits

A calibration mechanism is often desired in analog/RF circuits that are designed in advance process nodes which exhibit large process variation, so as to recover yield loss and obtain the best possible trade-off between performances. In this paper, we present a calibration approach based on embedded sensors that has several appealing attributes. Specifically, it is virtually applicable to any circuit, the calibration mechanism is totally non-intrusive and, thereby, it does not degrade the performances of the circuit, and the calibration is performed in one-shot requiring a single test step, thus the calibration time is kept at a minimum. The proposed calibration approach is demonstrated experimentally on a 65 nm RF power amplifier based on fabricated chips from two corner wafers and a typical wafer.

Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs

In this paper, a ternary stimulus is proposed for testing ΣΔ Analog-to-Digital Converters (ADCs). The ternary stimulus is composed of three logic levels {-1,0,1} and is obtained by adding a binary stream with a delayed version of itself. Only four switches are added to the input stage of the modulator of the ΣΔ ADC for facilitating the injection of the ternary stimulus. Compared to a binary stimulus, the ternary stimulus contains less quantization noise and allows measuring the SNDR of the ΣΔ ADC for the whole input dynamic range. We discuss the optimization of the ternary stimulus and we demonstrate its efficiency using behavioral simulations of a second-order switched-capacitor (SC) ΣΔ modulator.

Harnessing fabrication process signature for predicting yield across designs

Yield estimation is an indispensable piece of information at the onset of high-volume manufacturing (HVM) of a device. The increasing demand for faster time-to-market and for designs with growing quality requirements and complexity, requires a quick and successful yield estimation prior to HVM. Prior to commencing HVM, a few early silicon wafers are typically produced and subjected to thorough characterization. One of the objectives of such characterization is yield estimation with better accuracy than what pre-silicon Monte Carlo simulation may offer. In this work, we propose predicting yield of a device using information from a similar previous-generation device, which is manufactured in the same technology node and in the same fabrication facility. For this purpose, we rely on the Bayesian Model Fusion (BMF) technique. The effectiveness of the proposed methodology is evaluated using sizable industrial data from two RF devices in a 65nm technology.

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques

Accurate and efficient evaluation of alternative test methods is required for analog/mixed-signal circuits. To address this need, this article presents a semiautomated practical simulation flow specifically targeting circuits with long simulation times.