Manuel J. Barragan

Efficient selection of signatures for analog/RF alternate test

This work proposes a generic methodology for selecting meaningful subsets of indirect measurements (signatures). This allows precise predictions of the DUT performances and/or precise pass/fail classification of the DUT, while minimizing the number of necessary measurements. Two simple figures of merit are provided for ranking sets of signatures a priori, before training any machine learning model. These two figures evaluate the quality of each signature based on its Brownian distance correlation to the target specifications, and on its local distribution in the proximities of the pass/fail decision boundaries. The proposed methodology is illustrated by its direct application to a DC-based alternate test for LNAs.

On-Chip Analog Sinewave Generator with Reduced Circuitry Resources

This paper proposes an analog sinewave signal generator with minimal circuitry resources. It is based on a linear time variant filter that gives a high quality sine signal in response to a DC input. The proposed architecture has the attributes of digital programming and control capability, robustness and reduced area overhead, what make it suitable for BIST applications. Experimental results from a practical design demonstrate the feasibility of the approach.

Sine-Wave Signal Characterization Using Square-Wave and ΣΔ-Modulation: Application to Mixed-Signal BIST

This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. It is based on a double-modulation, square-wave and sigma-delta, together with a simple Digital Processing Algorithm. It leads to an efficient and robust approach very suitable for BIST applications. In this line, some considerations for on-chip implementation are addressed together with simulation results that validate the feasibility of the proposed approach.

A Procedure for Alternate Test Feature Design and Selection

This paper is a practical illustration of the adoption of alternate tests based upon the judicious selection of the set of parameters to be considered for design as well as to be observed subsequently. The notion of signatures is introduced, and their ability to predict design accuracy is analyzed. The application is demonstrated for an RF LNA circuit.

Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators—a continuous-time generator and a discrete-time one—have been integrated in a standard 0.35 μm CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.

Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs

This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.

Mostly-digital design of sinusoidal signal generators for mixed-signal BIST applications using harmonic cancellation

This work proposes a novel approach for the design of high-quality on-chip sinusoidal signal generators using digital circuitry. The proposed generation technique is based on a simple digital shift-register that provides a set of phase-shifted versions of a digital square-wave signal. These square-wave signals are conveniently combined using a harmonic cancellation strategy to yield a spectrally pure sinusoidal output signal. The proposed strategy allows cancelling low-frequency harmonics close to the fundamental component of the generated sinusoidal signal, while a simple first order low-pass filter is used to attenuate higher order harmonic components. A simple one-shot calibration strategy is also presented in order to compensate the effects of the main non-idealities affecting the dynamic linearity of the generator. Statistical behavioral simulations are provided to demonstrate the feasibility of the proposed generator.

Design of an on-chip stepwise ramp generator for ADC static BIST applications

This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main non-idealities affecting the linearity of the generator are discussed on a practical implementation in a 65nm CMOS technology. Electrical simulation results at transistor level are provided to verify the feasibility and performance of the proposed approach.

On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test

Linearity testing for ADCs is one of the most resource and time consuming tasks in the production test of a mixed-signal integrated system. Advanced strategies for reducing static test time, such as the reduced code linearity test technique, have been recently presented. However, the application of these techniques require a high linearity input stimulus to excite the ADC under test, which is usually provided by an external analog signal generator in the ATE. Extending the static linearity test to a BIST implementation requires to include this generator on-chip, which is a challenging task. This paper explores different possibilities for the on-chip implementation of such generators.

Practical implementation of a network analyzer for analog BIST applications

This paper presents a practical implementation of a network analyzer for analog BIST applications. The network analyzer consists of a sinewave generator and a sinewave evaluator based on switch-capacitor techniques. Both the generator and the evaluator have been integrated in a 0.35 mum CMOS technology. The functionality of the system has been proved in the lab. For this purpose, a demonstrator board has been developed including the proposed network analyzer and a filter as DUT Measurements in the lab demonstrate a dynamic range of 70dB in the frequency range up to 20 kHz.