Harmander Singh Deogun

Power Gating with Multiple Sleep Modes

This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. Our simulations and data traces show that multiple sleep mode capability provides an extra 17% reduction in overall leakage as compared to single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit

Simultaneous state, Vt and Tox assignment for total standby power minimization

Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. Also, gate oxide leakage current (I/sub gate/) has become comparable to subthreshold leakage (I/sub sub/) in 90 nm technologies. In this paper, we propose a new method that uses a combined approach of sleep-state, threshold voltage (V/sub t/ and gate oxide thickness (T/sub ox/) assignments in a dual-V/sub t/ and dual-T/sub ox/ process to minimize both I/sub sub/ and I/sub gate/. Using this method, total leakage current can be dramatically reduced since in a known state in standby mode, only certain transistors are responsible for leakage current and need to be considered for high-V/sub t/ or thick-T/sub ox/ assignment. We formulate the optimization problem for simultaneous state, V/sub t/ and T/sub ox/ assignments under delay constraints and propose two practical heuristics. We implemented and tested the proposed methods on a set of synthesized benchmark circuits. Results show an average leakage current reduction of 5a-6X and 2-3X compared to previous approaches that only use state or state+V/sub t/ assignment, respectively, with small delay penalties.

Leakage-and crosstalk-aware bus encoding for total power reduction

Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.

Gate-level mitigation techniques for neutron-induced soft error rate

Neutron-induced single-event upsets have become increasingly problematic in aggressively scaled process technologies due to smaller nodal capacitances and reduced operating voltages. We present a probability-based analysis of neutron strikes on combinational logic chains and investigate techniques to increase circuit robustness in terms of decreasing the probability of upsetting the capturing latch given a particle strike. We show that using a technique of inserting simple cross-coupled inverter pairs on error prone sites, as well as intelligently placing lower V/sub th/ devices and readjusting device width, can increase the robustness by nearly 20% thereby increasing the mean time between soft errors by almost 25%. This technique incurs substantially less overhead than traditional redundancy approaches to mitigating soft errors.

Bus encoding for total power reduction using a leakage-aware buffer configuration

Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We utilize a buffer design approach with a selective use of high-threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.

Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization

Increased buffer insertion along on-chip global lines and the increasing contribution of leakage power have resulted in buffer leakage emerging as one of the chief contributors to system leakage power. We present a novel power-gating scheme for repeaters on global bus lines that address the pressing problem of runtime leakage while simultaneously eliminating worst-case capacitive coupling between adjacent bus lines. We propose using a pulsed MTCMOS (multiple threshold CMOS) scheme that dynamically activates the bus system only when transmitting a signal. Additionally, a bus encoding scheme is used to eliminate worst-case coupling and thereby negate the power-gating and pulse generation performance penalty. We consider all sources of delay and leakage power, including that of the MTCMOS control circuitry. This technique can result in nearly a 30% reduction in total bus system power for low switching activities and up to 2.3 times reduction in standby mode leakage with no reactivation delay penalty.

A dual-V DD boosted pulsed bus technique for low power and low leakage operation

In this paper, we propose a new dual-VDD bus technique that is well suited for low power operation. This technique adapts a static pulsed bus architecture to use dual-VDD power supplies. During quiescent periods, the bus system idles at the lower of the two VDD supplies, thereby lowering static power dissipation. When actively transitioning, the inverters in the bus system are temporarily boosted to the higher VDD supply to provide the needed drive strength for performance. Since the VDD boosting is done in a pulsed manner, the bus system is in a high VDD state only when required, ensuring lower power operation without sacrificing performance. This technique yields up to a 50% reduction in total power over traditional static buses and up to a 35% reduction in total power over standard static pulsed buses, with a 12-15% delay improvement

Fine grained multi-threshold CMOS for enhanced leakage reduction

The exponential increase in leakage power due to technology scaling has made multi-threshold CMOS (MTCMOS) an attractive design style for low-power applications. We explore this design style in a datapath and introduce a fine grained power gating approach to better exploit the power-performance tradeoff. We propose a power gating technique where the degree of power gating applied becomes progressively stronger further along the datapath